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chip_ignite/.github/workflows/user_project_ci.yml
cah f391dae4f2
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ci: suppress remaining lint warnings (BLKSEQ, UNUSEDPARAM, CASEINCOMPLETE)
BLKSEQ: intentional blocking assigns in sequential logic for Yosys
BLKLOOPINIT compatibility. UNUSEDPARAM/CASEINCOMPLETE: known benign.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-03-14 00:23:33 -06:00

29 lines
700 B
YAML

name: CI
on:
push:
pull_request:
workflow_dispatch:
jobs:
rtl-lint:
timeout-minutes: 30
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v4
- name: Install Verilator
run: |
sudo apt-get update
sudo apt-get install -y verilator
- name: Lint RTL
run: |
verilator --lint-only -Wall \
--top-module ldpc_decoder_top \
-Wno-UNUSEDSIGNAL -Wno-UNDRIVEN -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC \
-Wno-UNUSEDPARAM -Wno-CASEINCOMPLETE -Wno-BLKSEQ \
verilog/rtl/ldpc_decoder_top.sv \
verilog/rtl/ldpc_decoder_core.sv \
verilog/rtl/wishbone_interface.sv