{
    "//": "Design files",
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/user_project_wrapper.v"
    ],
    "PNR_SDC_FILE": "dir::signoff.sdc",

    "//": "Hardening strategy variables (this is for 1-Macro-First Hardening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info",
    "SYNTH_ELABORATE_ONLY": true,
    "RUN_POST_GPL_DESIGN_REPAIR": false,
    "RUN_POST_CTS_RESIZER_TIMING": false,
    "DESIGN_REPAIR_BUFFER_INPUT_PORTS": false,
    "FP_PDN_ENABLE_RAILS": true,
    "RUN_ANTENNA_REPAIR": false,
    "RUN_FILL_INSERTION": true,
    "RUN_TAP_ENDCAP_INSERTION": true,
    "RUN_CTS": false,
    "RUN_IRDROP_REPORT": false,
    "ERROR_ON_SYNTH_CHECKS": false,
    "ERROR_ON_UNMAPPED_CELLS": false,
    "ERROR_ON_NL_ASSIGN_STATEMENTS": false,
    "ERROR_ON_MAGIC_DRC": true,
    "ERROR_ON_LVS_ERROR": false,
    "HOLD_VIOLATION_CORNERS": [""],

    "//": "Macros configurations",
    "MACROS": {
        "ldpc_decoder_top": {
            "gds": [
                "dir::../../gds/ldpc_decoder_top.gds"
            ],
            "lef": [
                "dir::../../lef/ldpc_decoder_top.lef"
            ],
            "instances": {
                "mprj": {
                    "location": [60, 15],
                    "orientation": "N"
                }
            },
            "nl": [
                "dir::../../verilog/gl/ldpc_decoder_top.v"
            ],
            "spef": {
                "min_*": [
                    "dir::../../spef/multicorner/ldpc_decoder_top.min.spef"
                ],
                "nom_*": [
                    "dir::../../spef/multicorner/ldpc_decoder_top.nom.spef"
                ],
                "max_*": [
                    "dir::../../spef/multicorner/ldpc_decoder_top.max.spef"
                ]
            },
            "lib": {
                "*": "dir::../../lib/ldpc_decoder_top.lib"
            }
        }
    },
    "PDN_MACRO_CONNECTIONS": ["mprj vccd2 vssd2 vccd1 vssd1"],

    "//": "PDN configurations",
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "FP_PDN_VWIDTH": 3.1,
    "FP_PDN_HWIDTH": 3.1,
    "FP_PDN_VSPACING": 15.5,
    "FP_PDN_HSPACING": 15.5,
    "FP_PDN_VPITCH": 180,
    "FP_PDN_HPITCH": 180,
    "ERROR_ON_PDN_VIOLATIONS": false,

    "//": "Magic variables",
    "MAGIC_DRC_USE_GDS": true,

    "DRT_THREADS": 1,
    "MAX_TRANSITION_CONSTRAINT": 1.5,

    "//": "Fixed configurations for caravel. You should NOT edit this section",
    "DESIGN_NAME": "user_project_wrapper",
    "FP_SIZING": "absolute",
    "DIE_AREA": [0, 0, 2920, 3520],
    "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
    "VDD_NETS": [
        "vccd1",
        "vccd2",
        "vdda1",
        "vdda2"
    ],
    "GND_NETS": [
        "vssd1",
        "vssd2",
        "vssa1",
        "vssa2"
    ],
    "FP_PDN_CORE_RING": true,
    "FP_PDN_CORE_RING_VWIDTH": 3.1,
    "FP_PDN_CORE_RING_HWIDTH": 3.1,
    "FP_PDN_CORE_RING_VOFFSET": 12.45,
    "FP_PDN_CORE_RING_HOFFSET": 12.45,
    "FP_PDN_CORE_RING_VSPACING": 1.7,
    "FP_PDN_CORE_RING_HSPACING": 1.7,
    "CLOCK_PORT": "wb_clk_i",
    "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
    "MAGIC_DEF_LABELS": false,
    "CLOCK_PERIOD": 25,
    "MAGIC_ZEROIZE_ORIGIN": false,
    "meta": {
        "version": 2
    }
}
