{
    "DESIGN_NAME": "user_proj_example",
    "FP_PDN_MULTILAYER": false,
    "VERILOG_FILES": [
        "dir::../../verilog/rtl/defines.v",
        "dir::../../verilog/rtl/user_proj_example.v"
    ],
    "CLOCK_PERIOD": 25,
    "CLOCK_PORT": "wb_clk_i",
    "CLOCK_NET": "counter.clk",
    "FP_SIZING": "absolute",
    "DIE_AREA": [
        0,
        0,
        2800,
        1760
    ],
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "MAX_TRANSITION_CONSTRAINT": 1.0,
    "MAX_FANOUT_CONSTRAINT": 16,
    "PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
    "GRT_RESIZER_SETUP_SLACK_MARGIN": 0.2,
    "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.2,
    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
    "CTS_CLK_MAX_WIRE_LENGTH": 500,
    "MAGIC_DEF_LABELS": false,
    "SYNTH_ABC_BUFFERING": false,
    "RUN_HEURISTIC_DIODE_INSERTION": true,
    "HEURISTIC_ANTENNA_THRESHOLD": 110,
    "RUN_ANTENNA_REPAIR": true,
    "RUN_POST_GRT_DESIGN_REPAIR": true,
    "RUN_POST_GRT_RESIZER_TIMING": true,
    "VDD_NETS": [
        "vccd1"
    ],
    "GND_NETS": [
        "vssd1"
    ],
    "FALLBACK_SDC_FILE": "dir::base_user_proj_example.sdc",
    "MAGIC_DRC_USE_GDS": true,
    "DPL_CELL_PADDING": 2,
    "GPL_CELL_PADDING": 2,
    "pdk::sky130*": {
        "RT_MAX_LAYER": "met4",
        "scl::sky130_fd_sc_hd": {
            "CLOCK_PERIOD": 25
        },
        "scl::sky130_fd_sc_hdll": {
            "CLOCK_PERIOD": 10
        },
        "scl::sky130_fd_sc_hs": {
            "CLOCK_PERIOD": 8
        },
        "scl::sky130_fd_sc_ls": {
            "CLOCK_PERIOD": 10,
            "SYNTH_MAX_FANOUT": 5
        },
        "scl::sky130_fd_sc_ms": {
            "CLOCK_PERIOD": 10
        }
    },
    "pdk::gf180mcuC": {
        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
        "CLOCK_PERIOD": 24.0,
        "RT_MAX_LAYER": "Metal4",
        "SYNTH_MAX_FANOUT": 4,
        "PL_TARGET_DENSITY_PCT": 45
    },
    "meta": {
        "version": 2
    }
}
