Initial commit

2026-02-23 20:42:11 -07:00
commit 2ba96a115d
462 changed files with 9166588 additions and 0 deletions
--- a/openlane/.gitignore
+++ b/openlane/.gitignore
@@ -0,0 +1,4 @@
+*/runs
+default.cvcrc
+.venv/
+.version-*
--- a/openlane/Makefile
+++ b/openlane/Makefile
@@ -0,0 +1,116 @@
+# Copyright 2025 UmbraLogic Technologies LLC
+#
+# Adapted from Caravel User Project
+#
+# Copyright 2020-2024 Efabless Corporation
+# SPDX-FileCopyrightText:
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+MAKEFLAGS += --warn-undefined-variables
+
+# set shell to bash
+SHELL := /bin/bash
+
+ifeq ($(origin LIBRELANE_RUN_TAG), undefined)
+export LIBRELANE_RUN_TAG := $(shell date '+%y_%m_%d_%H_%M')
+endif
+ifeq ($(origin CF_LIBRELANE_TAG), undefined)
+export CF_LIBRELANE_TAG := CI2511
+endif
+
+export CARAVEL_ROOT := $(CARAVEL_ROOT)
+export PDK := $(PDK)
+export PDK_ROOT := $(PDK_ROOT)
+
+designs = $(shell cd $(PROJECT_ROOT)/openlane && find * -maxdepth 0 -type d)
+current_design = null
+
+LIBRELANE_USE_NIX ?= 0
+
+librelane_args = \
+	--run-tag $(LIBRELANE_RUN_TAG) \
+	--manual-pdk \
+	--pdk-root $(PDK_ROOT) \
+	--pdk $(PDK)
+
+docker_mounts = \
+	-m $(PROJECT_ROOT) \
+	-m $(PDK_ROOT) \
+	-m $(CARAVEL_ROOT) \
+	-m $(HOME)/.ipm
+
+ifneq ($(MCW_ROOT),)
+export MCW_ROOT:=$(MCW_ROOT)
+docker_mounts += -m $(MCW_ROOT)
+endif
+
+ifeq ($(LIBRELANE_USE_NIX),1)
+ifeq ($(origin UPSTREAM_LIBRELANE_TAG), undefined)
+librelane_run = nix run github:chipfoundry/openlane-2/$(CF_LIBRELANE_TAG) --
+else
+librelane_run = nix run github:librelane/librelane/$(UPSTREAM_LIBRELANE_TAG) --
+endif
+else
+librelane_docker_args = $(shell test -t 0 || echo "--docker-no-tty")
+librelane_run = $(PROJECT_ROOT)/openlane/.venv/bin/python3 -m librelane $(docker_mounts) $(librelane_docker_args) --dockerized 
+endif
+
+list:
+	@echo $(designs)
+
+.PHONY: $(designs)
+$(designs) : export current_design=$@
+$(designs):
+	@config_dir="$(PROJECT_ROOT)/openlane/$@"; \
+	config=""; \
+	for ext in yaml json tcl; do \
+		if [ -f "$$config_dir/config.$$ext" ]; then \
+			config="$$config_dir/config.$$ext"; break; \
+		fi; \
+	done; \
+	if [ -n "$$config" ]; then \
+		cmd='$(librelane_run) $(librelane_args) --ef-save-views-to $(PROJECT_ROOT) --overwrite "$$config"'; \
+		echo "* Running LibreLane on $@ with $$config"; \
+		echo $$cmd; \
+		eval $$cmd; \
+	fi
+
+librelane: librelane-venv librelane-docker-image
+
+.PHONY: librelane-docker-image
+librelane-docker-image:
+	@echo "LibreLane will automatically pull the appropriate Docker image as needed."
+
+librelane-venv: $(PROJECT_ROOT)/openlane/.venv/manifest.txt
+$(PROJECT_ROOT)/openlane/.venv/manifest.txt: $(PROJECT_ROOT)/openlane/.version-$(CF_LIBRELANE_TAG)
+	rm -rf $(PROJECT_ROOT)/openlane/.venv
+	python3 -m venv $(PROJECT_ROOT)/openlane/.venv
+	PYTHONPATH= $(PROJECT_ROOT)/openlane/.venv/bin/python3 -m pip install --upgrade pip
+	PYTHONPATH= $(PROJECT_ROOT)/openlane/.venv/bin/python3 -m pip install "https://github.com/chipfoundry/openlane-2/tarball/$(CF_LIBRELANE_TAG)"
+	PYTHONPATH= $(PROJECT_ROOT)/openlane/.venv/bin/python3 -m pip freeze > $@
+	
+$(PROJECT_ROOT)/openlane/.version-$(CF_LIBRELANE_TAG):
+	echo "$(CF_LIBRELANE_TAG)" > $@
+	python3 -c 'import os; [os.remove(f) for f in os.listdir("$(@D)") if f.startswith(".version-") and f != os.path.basename("$@")]'
+
+.PHONY: librelane-nix
+librelane-nix:
+	@if ! command -v nix > /dev/null; then\
+		echo "Nix not found. Please install Nix using the LibreLane documentation:"; \
+		echo "	https://librelane.readthedocs.io/en/latest/getting_started/common/nix_installation/index.html"; \
+	else \
+		echo "Activating LibreLane Nix environment…"; \
+		nix develop github:chipfoundry/openlane-2/$(CF_LIBRELANE_TAG); \
+	fi
--- a/openlane/copy_views.sh
+++ b/openlane/copy_views.sh
@@ -0,0 +1,57 @@
+#!/bin/bash
+
+# Check if the correct number of arguments are passed
+if [ "$#" -ne 3 ]; then
+    echo "Usage: $0 PROJECT_ROOT MACRO RUN_TAG"
+    exit 1
+fi
+
+# Assign arguments to variables
+PROJECT_ROOT=$1
+MACRO=$2
+RUN_TAG=$3
+
+# Create directory for timing reports
+mkdir -p "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/timing-reports"
+
+# Copy CSV files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/metrics.csv" "${PROJECT_ROOT}/signoff/${MACRO}/"
+
+# Copy DEF files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/def/${MACRO}.def" "${PROJECT_ROOT}/def/${MACRO}.def"
+
+# Copy SDC files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/sdc/${MACRO}.sdc" "${PROJECT_ROOT}/sdc/${MACRO}.sdc"
+
+# Copy GDS files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/gds/${MACRO}.gds" "${PROJECT_ROOT}/gds/${MACRO}.gds"
+
+# Copy LEF files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/lef/${MACRO}.lef" "${PROJECT_ROOT}/lef/${MACRO}.lef"
+
+# Copy MAG files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"magic-streamout/${MACRO}.mag" "${PROJECT_ROOT}/mag/${MACRO}.mag"
+
+# Copy Verilog files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/pnl/${MACRO}.pnl.v" "${PROJECT_ROOT}/verilog/gl/${MACRO}.v"
+
+
+# Copy SPEF files (nominal, minimum, maximum)
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/spef/nom/"* "${PROJECT_ROOT}/spef/multicorner/${MACRO}.nom.spef"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/spef/nom/"* "${PROJECT_ROOT}/spef/${MACRO}.spef"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/spef/min/"* "${PROJECT_ROOT}/spef/multicorner/${MACRO}.min.spef"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/spef/max/"* "${PROJECT_ROOT}/spef/multicorner/${MACRO}.max.spef"
+
+# Copy LIB files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/lib/nom"*"tt"*"/"* "${PROJECT_ROOT}/lib/${MACRO}.lib"
+
+# Copy resolved.json
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/resolved.json" "${PROJECT_ROOT}/signoff/${MACRO}/"
+
+# Copy DRC, LVS reports, and logs
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"magic-drc/reports/"* "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"netgen-lvs/reports/"*".rpt" "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"netgen-lvs/netgen-lvs.log" "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/"
+
+# Copy STA post PnR summary report
+cp -r "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"openroad-stapostpnr/summary.rpt" "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/timing-reports/"
--- a/openlane/user_proj_example/base_user_proj_example.sdc
+++ b/openlane/user_proj_example/base_user_proj_example.sdc
@@ -0,0 +1,145 @@
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+set ::env(IO_SYNC) 0
+# Clock network
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]
--- a/openlane/user_proj_example/config.json
+++ b/openlane/user_proj_example/config.json
@@ -0,0 +1,72 @@
+{
+    "DESIGN_NAME": "user_proj_example",
+    "FP_PDN_MULTILAYER": false,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/user_proj_example.v"
+    ],
+    "CLOCK_PERIOD": 25,
+    "CLOCK_PORT": "wb_clk_i",
+    "CLOCK_NET": "counter.clk",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": [
+        0,
+        0,
+        2800,
+        1760
+    ],
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "MAX_TRANSITION_CONSTRAINT": 1.0,
+    "MAX_FANOUT_CONSTRAINT": 16,
+    "PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
+    "GRT_RESIZER_SETUP_SLACK_MARGIN": 0.2,
+    "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.2,
+    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
+    "CTS_CLK_MAX_WIRE_LENGTH": 500,
+    "MAGIC_DEF_LABELS": false,
+    "SYNTH_ABC_BUFFERING": false,
+    "RUN_HEURISTIC_DIODE_INSERTION": true,
+    "HEURISTIC_ANTENNA_THRESHOLD": 110,
+    "RUN_ANTENNA_REPAIR": true,
+    "RUN_POST_GRT_DESIGN_REPAIR": true,
+    "RUN_POST_GRT_RESIZER_TIMING": true,
+    "VDD_NETS": [
+        "vccd1"
+    ],
+    "GND_NETS": [
+        "vssd1"
+    ],
+    "FALLBACK_SDC_FILE": "dir::base_user_proj_example.sdc",
+    "MAGIC_DRC_USE_GDS": true,
+    "DPL_CELL_PADDING": 2,
+    "GPL_CELL_PADDING": 2,
+    "pdk::sky130*": {
+        "RT_MAX_LAYER": "met4",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 25
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "pdk::gf180mcuC": {
+        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+        "CLOCK_PERIOD": 24.0,
+        "RT_MAX_LAYER": "Metal4",
+        "SYNTH_MAX_FANOUT": 4,
+        "PL_TARGET_DENSITY_PCT": 45
+    },
+    "meta": {
+        "version": 2
+    }
+}
--- a/openlane/user_proj_example/pin_order.cfg
+++ b/openlane/user_proj_example/pin_order.cfg
@@ -0,0 +1,59 @@
+#BUS_SORT
+
+#S
+wb_.*
+wbs_.*
+la_.*
+irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+
+#WR
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]
--- a/openlane/user_project_wrapper/config.json
+++ b/openlane/user_project_wrapper/config.json
@@ -0,0 +1,107 @@
+{
+    "//": "Design files",
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/user_project_wrapper.v"
+    ],
+    "PNR_SDC_FILE": "dir::signoff.sdc",
+    
+    "//": "Hardening strategy variables (this is for 1-Macro-First Hardening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info",
+    "SYNTH_ELABORATE_ONLY": true,
+    "RUN_POST_GPL_DESIGN_REPAIR": false,
+    "RUN_POST_CTS_RESIZER_TIMING": false,
+    "DESIGN_REPAIR_BUFFER_INPUT_PORTS": false,
+    "FP_PDN_ENABLE_RAILS": false,
+    "RUN_ANTENNA_REPAIR": false,
+    "RUN_FILL_INSERTION": false,
+    "RUN_TAP_ENDCAP_INSERTION": false,
+    "RUN_CTS": false,
+    "RUN_IRDROP_REPORT": false,
+    "ERROR_ON_SYNTH_CHECKS": false,
+
+    "//": "Macros configurations",
+    "MACROS": {
+        "user_proj_example": {
+            "gds": [
+                "dir::../../gds/user_proj_example.gds"
+            ],
+            "lef": [
+                "dir::../../lef/user_proj_example.lef"
+            ],
+            "instances": {
+                "mprj": {
+                    "location": [60, 15],
+                    "orientation": "N"
+                }
+            },
+            "nl": [
+                "dir::../../verilog/gl/user_proj_example.v"
+            ],
+            "spef": {
+                "min_*": [
+                    "dir::../../spef/multicorner/user_proj_example.min.spef"
+                ],
+                "nom_*": [
+                    "dir::../../spef/multicorner/user_proj_example.nom.spef"
+                ],
+                "max_*": [
+                    "dir::../../spef/multicorner/user_proj_example.max.spef"
+                ]
+            },
+            "lib": {
+                "*": "dir::../../lib/user_proj_example.lib"
+            }
+        }
+    },
+    "PDN_MACRO_CONNECTIONS": ["mprj vccd2 vssd2 vccd1 vssd1"],
+
+    "//": "PDN configurations",
+    "FP_PDN_VOFFSET": 5,
+    "FP_PDN_HOFFSET": 5,
+    "FP_PDN_VWIDTH": 3.1,
+    "FP_PDN_HWIDTH": 3.1,
+    "FP_PDN_VSPACING": 15.5,
+    "FP_PDN_HSPACING": 15.5,
+    "FP_PDN_VPITCH": 180,
+    "FP_PDN_HPITCH": 180,
+    "ERROR_ON_PDN_VIOLATIONS": false,
+
+    "//": "Magic variables",
+    "MAGIC_DRC_USE_GDS": true,
+
+    "DRT_THREADS": 1,
+    "MAX_TRANSITION_CONSTRAINT": 1.5,
+
+    "//": "Fixed configurations for caravel. You should NOT edit this section",
+    "DESIGN_NAME": "user_project_wrapper",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": [0, 0, 2920, 3520],
+    "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
+    "VDD_NETS": [
+        "vccd1",
+        "vccd2",
+        "vdda1",
+        "vdda2"
+    ],
+    "GND_NETS": [
+        "vssd1",
+        "vssd2",
+        "vssa1",
+        "vssa2"
+    ],
+    "FP_PDN_CORE_RING": true,
+    "FP_PDN_CORE_RING_VWIDTH": 3.1,
+    "FP_PDN_CORE_RING_HWIDTH": 3.1,
+    "FP_PDN_CORE_RING_VOFFSET": 12.45,
+    "FP_PDN_CORE_RING_HOFFSET": 12.45,
+    "FP_PDN_CORE_RING_VSPACING": 1.7,
+    "FP_PDN_CORE_RING_HSPACING": 1.7,
+    "CLOCK_PORT": "wb_clk_i",
+    "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
+    "MAGIC_DEF_LABELS": false,
+    "CLOCK_PERIOD": 25,
+    "MAGIC_ZEROIZE_ORIGIN": false,
+    "meta": {
+        "version": 2
+    }
+}
--- a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper.def
--- a/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def
+++ b/openlane/user_project_wrapper/fixed_dont_change/user_project_wrapper_gf180mcu.def
--- a/openlane/user_project_wrapper/signoff.sdc
+++ b/openlane/user_project_wrapper/signoff.sdc
@@ -0,0 +1,145 @@
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+set ::env(IO_SYNC) 0
+# Clock network
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]
--- a/openlane/user_project_wrapper/vsrc/upw_vccd1_vsrc.loc
+++ b/openlane/user_project_wrapper/vsrc/upw_vccd1_vsrc.loc
@@ -0,0 +1,3 @@
+2911.7,3148.92,24,1.8
+2911.7,3198.92,24,1.8
+2911.7,932.65,24,1.8
--- a/openlane/user_project_wrapper/vsrc/upw_vccd2_vsrc.loc
+++ b/openlane/user_project_wrapper/vsrc/upw_vccd2_vsrc.loc
@@ -0,0 +1,3 @@
+8.30,3169.21,24,1.8
+8.30,3219.21,24,1.8
+8.30,839.94,24,1.8
--- a/openlane/user_project_wrapper/vsrc/upw_vdda1_vsrc.loc
+++ b/openlane/user_project_wrapper/vsrc/upw_vdda1_vsrc.loc
@@ -0,0 +1,4 @@
+2911.70,1126.15,24,3.3
+2911.70,1176.15,24,3.3
+2911.70,2702.81,24,3.3
+2911.70,2752.81,24,3.3
--- a/openlane/user_project_wrapper/vsrc/upw_vdda2_vsrc.loc
+++ b/openlane/user_project_wrapper/vsrc/upw_vdda2_vsrc.loc
@@ -0,0 +1,2 @@
+8.30,1024.44,24,3.3
+8.30,1074.44,24,3.3
--- a/openlane/user_project_wrapper/vsrc/upw_vssa1_vsrc.loc
+++ b/openlane/user_project_wrapper/vsrc/upw_vssa1_vsrc.loc
@@ -0,0 +1,4 @@
+2911.7,684.15,24,0.0
+2911.7,734.15,24,0.0
+2552.97,3511.70,24,0.0
+2602.97,3511.70,24,0.0
--- a/openlane/user_project_wrapper/vsrc/upw_vssa2_vsrc.loc
+++ b/openlane/user_project_wrapper/vsrc/upw_vssa2_vsrc.loc
@@ -0,0 +1,2 @@
+8.30,2747.21,24,0.0
+8.30,2797.21,24,0.0
--- a/openlane/user_project_wrapper/vsrc/upw_vssd1_vsrc.loc
+++ b/openlane/user_project_wrapper/vsrc/upw_vssd1_vsrc.loc
@@ -0,0 +1,3 @@
+2911.7,907.15,24,0.0
+2911.7,957.15,24,0.0
+2911.7,3174.42,24,0.0
--- a/openlane/user_project_wrapper/vsrc/upw_vssd2_vsrc.loc
+++ b/openlane/user_project_wrapper/vsrc/upw_vssd2_vsrc.loc
@@ -0,0 +1,3 @@
+8.30,814.44,24,0.0
+8.30,864.44,24,0.0
+8.30,3194.71,24,0.0