Initial commit
This commit is contained in:
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287
signoff/user_proj_example/metrics.csv
Normal file
287
signoff/user_proj_example/metrics.csv
Normal file
@@ -0,0 +1,287 @@
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||||
Metric,Value
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||||
design__lint_error__count,0
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||||
design__lint_timing_construct__count,0
|
||||
design__lint_warning__count,8
|
||||
design__inferred_latch__count,0
|
||||
design__instance__count,70590
|
||||
design__instance__area,95369
|
||||
design__instance_unmapped__count,0
|
||||
synthesis__check_error__count,0
|
||||
design__max_slew_violation__count__corner:nom_tt_025C_1v80,4
|
||||
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,14
|
||||
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
|
||||
power__internal__total,0.00019559991778805852
|
||||
power__switching__total,0.000429551990237087
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||||
power__leakage__total,1.919598524580124E-8
|
||||
power__total,0.000625171116553247
|
||||
clock__skew__worst_hold__corner:nom_tt_025C_1v80,-2.096730848291461
|
||||
clock__skew__worst_setup__corner:nom_tt_025C_1v80,3.154773864771945
|
||||
timing__hold__ws__corner:nom_tt_025C_1v80,0.3478915032298054
|
||||
timing__setup__ws__corner:nom_tt_025C_1v80,7.060046969096608
|
||||
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
|
||||
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
|
||||
timing__hold__wns__corner:nom_tt_025C_1v80,0
|
||||
timing__setup__wns__corner:nom_tt_025C_1v80,0.0
|
||||
timing__hold_vio__count__corner:nom_tt_025C_1v80,0
|
||||
timing__hold_r2r__ws__corner:nom_tt_025C_1v80,1.019479
|
||||
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
|
||||
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
|
||||
timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
|
||||
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
|
||||
design__max_slew_violation__count__corner:nom_ss_100C_1v60,174
|
||||
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,14
|
||||
design__max_cap_violation__count__corner:nom_ss_100C_1v60,1
|
||||
clock__skew__worst_hold__corner:nom_ss_100C_1v60,-2.0973783303777345
|
||||
clock__skew__worst_setup__corner:nom_ss_100C_1v60,3.0085152998174016
|
||||
timing__hold__ws__corner:nom_ss_100C_1v60,1.0258354456252161
|
||||
timing__setup__ws__corner:nom_ss_100C_1v60,2.4240024007463363
|
||||
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
|
||||
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
|
||||
timing__hold__wns__corner:nom_ss_100C_1v60,0
|
||||
timing__setup__wns__corner:nom_ss_100C_1v60,0.0
|
||||
timing__hold_vio__count__corner:nom_ss_100C_1v60,0
|
||||
timing__hold_r2r__ws__corner:nom_ss_100C_1v60,2.235596
|
||||
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
|
||||
timing__setup_vio__count__corner:nom_ss_100C_1v60,0
|
||||
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
|
||||
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
|
||||
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
|
||||
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,14
|
||||
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
|
||||
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-2.0964635065795703
|
||||
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,3.25268488017196
|
||||
timing__hold__ws__corner:nom_ff_n40C_1v95,0.25673464081342046
|
||||
timing__setup__ws__corner:nom_ff_n40C_1v95,8.431948711247525
|
||||
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
|
||||
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
|
||||
timing__hold__wns__corner:nom_ff_n40C_1v95,0
|
||||
timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
|
||||
timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
|
||||
timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.587006
|
||||
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
|
||||
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
|
||||
timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
|
||||
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
|
||||
design__max_slew_violation__count,192
|
||||
design__max_fanout_violation__count,14
|
||||
design__max_cap_violation__count,1
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||||
clock__skew__worst_hold,-2.094480648201511
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clock__skew__worst_setup,3.0075507380263278
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timing__hold__ws,0.24338487469856057
|
||||
timing__setup__ws,2.391910737178117
|
||||
timing__hold__tns,0.0
|
||||
timing__setup__tns,0.0
|
||||
timing__hold__wns,0
|
||||
timing__setup__wns,0.0
|
||||
timing__hold_vio__count,0
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||||
timing__hold_r2r__ws,0.571341
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||||
timing__hold_r2r_vio__count,0
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||||
timing__setup_vio__count,0
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||||
timing__setup_r2r__ws,inf
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||||
timing__setup_r2r_vio__count,0
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||||
design__die__bbox,0.0 0.0 2800.0 1760.0
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design__core__bbox,5.52 10.88 2794.04 1748.96
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design__io,543
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design__die__area,4.928E+6
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design__core__area,4.84667E+6
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design__instance__count__stdcell,70590
|
||||
design__instance__area__stdcell,95369
|
||||
design__instance__count__macros,0
|
||||
design__instance__area__macros,0
|
||||
design__instance__utilization,0.0196772
|
||||
design__instance__utilization__stdcell,0.0196772
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||||
design__instance__count__class:buffer,32
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||||
design__instance__count__class:inverter,7
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||||
design__instance__count__class:sequential_cell,33
|
||||
design__instance__count__class:multi_input_combinational_cell,273
|
||||
flow__warnings__count,1
|
||||
flow__errors__count,0
|
||||
design__instance__count__class:fill_cell,485362
|
||||
design__instance__count__class:tap_cell,69228
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||||
design__power_grid_violation__count__net:vccd1,0
|
||||
design__power_grid_violation__count__net:vssd1,0
|
||||
design__power_grid_violation__count,0
|
||||
timing__drv__floating__nets,0
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||||
timing__drv__floating__pins,0
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||||
design__instance__displacement__total,0
|
||||
design__instance__displacement__mean,0
|
||||
design__instance__displacement__max,0
|
||||
route__wirelength__estimated,101712
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||||
design__violations,0
|
||||
design__instance__count__class:timing_repair_buffer,362
|
||||
design__instance__count__class:clock_buffer,11
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||||
design__instance__count__setup_buffer,0
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||||
design__instance__count__hold_buffer,0
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||||
antenna__violating__nets,4
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||||
antenna__violating__pins,4
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||||
route__antenna_violation__count,4
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||||
design__instance__count__class:antenna_cell,644
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||||
antenna_diodes_count,2
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||||
route__net,1060
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||||
route__net__special,2
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||||
route__drc_errors__iter:1,198
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||||
route__wirelength__iter:1,102911
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||||
route__drc_errors__iter:2,82
|
||||
route__wirelength__iter:2,102825
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||||
route__drc_errors__iter:3,84
|
||||
route__wirelength__iter:3,102834
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||||
route__drc_errors__iter:4,5
|
||||
route__wirelength__iter:4,102805
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||||
route__drc_errors__iter:5,0
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||||
route__wirelength__iter:5,102803
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||||
route__drc_errors,0
|
||||
route__wirelength,102803
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||||
route__vias,4853
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||||
route__vias__singlecut,4853
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||||
route__vias__multicut,0
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||||
design__disconnected_pin__count,286
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||||
design__critical_disconnected_pin__count,0
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||||
route__wirelength__max,3004.91
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||||
timing__unannotated_net__count__corner:nom_tt_025C_1v80,420
|
||||
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
|
||||
timing__unannotated_net__count__corner:nom_ss_100C_1v60,420
|
||||
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
|
||||
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,420
|
||||
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
|
||||
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
|
||||
design__max_fanout_violation__count__corner:min_tt_025C_1v80,14
|
||||
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
|
||||
clock__skew__worst_hold__corner:min_tt_025C_1v80,-2.0946271976449062
|
||||
clock__skew__worst_setup__corner:min_tt_025C_1v80,3.166766494223121
|
||||
timing__hold__ws__corner:min_tt_025C_1v80,0.4132969639063154
|
||||
timing__setup__ws__corner:min_tt_025C_1v80,7.087754583861198
|
||||
timing__hold__tns__corner:min_tt_025C_1v80,0.0
|
||||
timing__setup__tns__corner:min_tt_025C_1v80,0.0
|
||||
timing__hold__wns__corner:min_tt_025C_1v80,0
|
||||
timing__setup__wns__corner:min_tt_025C_1v80,0.0
|
||||
timing__hold_vio__count__corner:min_tt_025C_1v80,0
|
||||
timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.992008
|
||||
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
|
||||
timing__setup_vio__count__corner:min_tt_025C_1v80,0
|
||||
timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
|
||||
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
|
||||
timing__unannotated_net__count__corner:min_tt_025C_1v80,420
|
||||
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
|
||||
design__max_slew_violation__count__corner:min_ss_100C_1v60,120
|
||||
design__max_fanout_violation__count__corner:min_ss_100C_1v60,14
|
||||
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
|
||||
clock__skew__worst_hold__corner:min_ss_100C_1v60,-2.095250254823947
|
||||
clock__skew__worst_setup__corner:min_ss_100C_1v60,3.037091553101025
|
||||
timing__hold__ws__corner:min_ss_100C_1v60,1.141694771038144
|
||||
timing__setup__ws__corner:min_ss_100C_1v60,2.494424293279187
|
||||
timing__hold__tns__corner:min_ss_100C_1v60,0.0
|
||||
timing__setup__tns__corner:min_ss_100C_1v60,0.0
|
||||
timing__hold__wns__corner:min_ss_100C_1v60,0
|
||||
timing__setup__wns__corner:min_ss_100C_1v60,0.0
|
||||
timing__hold_vio__count__corner:min_ss_100C_1v60,0
|
||||
timing__hold_r2r__ws__corner:min_ss_100C_1v60,2.180077
|
||||
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
|
||||
timing__setup_vio__count__corner:min_ss_100C_1v60,0
|
||||
timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
|
||||
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
|
||||
timing__unannotated_net__count__corner:min_ss_100C_1v60,420
|
||||
timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
|
||||
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
|
||||
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,14
|
||||
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
|
||||
clock__skew__worst_hold__corner:min_ff_n40C_1v95,-2.094480648201511
|
||||
clock__skew__worst_setup__corner:min_ff_n40C_1v95,3.2570613794588086
|
||||
timing__hold__ws__corner:min_ff_n40C_1v95,0.3001150524152958
|
||||
timing__setup__ws__corner:min_ff_n40C_1v95,8.453670003294032
|
||||
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
|
||||
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
|
||||
timing__hold__wns__corner:min_ff_n40C_1v95,0
|
||||
timing__setup__wns__corner:min_ff_n40C_1v95,0.0
|
||||
timing__hold_vio__count__corner:min_ff_n40C_1v95,0
|
||||
timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.571341
|
||||
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
|
||||
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
|
||||
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
|
||||
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
|
||||
timing__unannotated_net__count__corner:min_ff_n40C_1v95,420
|
||||
timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
|
||||
design__max_slew_violation__count__corner:max_tt_025C_1v80,12
|
||||
design__max_fanout_violation__count__corner:max_tt_025C_1v80,14
|
||||
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
|
||||
clock__skew__worst_hold__corner:max_tt_025C_1v80,-2.1012268075791374
|
||||
clock__skew__worst_setup__corner:max_tt_025C_1v80,3.160448436855897
|
||||
timing__hold__ws__corner:max_tt_025C_1v80,0.3314753010342061
|
||||
timing__setup__ws__corner:max_tt_025C_1v80,7.0523784364040365
|
||||
timing__hold__tns__corner:max_tt_025C_1v80,0.0
|
||||
timing__setup__tns__corner:max_tt_025C_1v80,0.0
|
||||
timing__hold__wns__corner:max_tt_025C_1v80,0
|
||||
timing__setup__wns__corner:max_tt_025C_1v80,0.0
|
||||
timing__hold_vio__count__corner:max_tt_025C_1v80,0
|
||||
timing__hold_r2r__ws__corner:max_tt_025C_1v80,1.026777
|
||||
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
|
||||
timing__setup_vio__count__corner:max_tt_025C_1v80,0
|
||||
timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
|
||||
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
|
||||
timing__unannotated_net__count__corner:max_tt_025C_1v80,420
|
||||
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
|
||||
design__max_slew_violation__count__corner:max_ss_100C_1v60,192
|
||||
design__max_fanout_violation__count__corner:max_ss_100C_1v60,14
|
||||
design__max_cap_violation__count__corner:max_ss_100C_1v60,1
|
||||
clock__skew__worst_hold__corner:max_ss_100C_1v60,-2.101982647435679
|
||||
clock__skew__worst_setup__corner:max_ss_100C_1v60,3.0075507380263278
|
||||
timing__hold__ws__corner:max_ss_100C_1v60,1.0005818679036624
|
||||
timing__setup__ws__corner:max_ss_100C_1v60,2.391910737178117
|
||||
timing__hold__tns__corner:max_ss_100C_1v60,0.0
|
||||
timing__setup__tns__corner:max_ss_100C_1v60,0.0
|
||||
timing__hold__wns__corner:max_ss_100C_1v60,0
|
||||
timing__setup__wns__corner:max_ss_100C_1v60,0.0
|
||||
timing__hold_vio__count__corner:max_ss_100C_1v60,0
|
||||
timing__hold_r2r__ws__corner:max_ss_100C_1v60,2.250683
|
||||
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
|
||||
timing__setup_vio__count__corner:max_ss_100C_1v60,0
|
||||
timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
|
||||
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
|
||||
timing__unannotated_net__count__corner:max_ss_100C_1v60,420
|
||||
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
|
||||
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
|
||||
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,14
|
||||
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
|
||||
clock__skew__worst_hold__corner:max_ff_n40C_1v95,-2.1008075873531826
|
||||
clock__skew__worst_setup__corner:max_ff_n40C_1v95,3.259567374940867
|
||||
timing__hold__ws__corner:max_ff_n40C_1v95,0.24338487469856057
|
||||
timing__setup__ws__corner:max_ff_n40C_1v95,8.420825164404606
|
||||
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
|
||||
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
|
||||
timing__hold__wns__corner:max_ff_n40C_1v95,0
|
||||
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
|
||||
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
|
||||
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.591791
|
||||
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
|
||||
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
|
||||
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
|
||||
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
|
||||
timing__unannotated_net__count__corner:max_ff_n40C_1v95,420
|
||||
timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
|
||||
timing__unannotated_net__count,420
|
||||
timing__unannotated_net_filtered__count,0
|
||||
design_powergrid__voltage__worst__net:vccd1__corner:nom_tt_025C_1v80,1.79983
|
||||
design_powergrid__drop__average__net:vccd1__corner:nom_tt_025C_1v80,1.8
|
||||
design_powergrid__drop__worst__net:vccd1__corner:nom_tt_025C_1v80,0.000166719
|
||||
design_powergrid__voltage__worst__net:vssd1__corner:nom_tt_025C_1v80,0.000205177
|
||||
design_powergrid__drop__average__net:vssd1__corner:nom_tt_025C_1v80,2.51703E-7
|
||||
design_powergrid__drop__worst__net:vssd1__corner:nom_tt_025C_1v80,0.000205177
|
||||
design_powergrid__voltage__worst,0.000205177
|
||||
design_powergrid__voltage__worst__net:vccd1,1.79983
|
||||
design_powergrid__drop__worst,0.000205177
|
||||
design_powergrid__drop__worst__net:vccd1,0.000166719
|
||||
design_powergrid__voltage__worst__net:vssd1,0.000205177
|
||||
design_powergrid__drop__worst__net:vssd1,0.000205177
|
||||
ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
|
||||
ir__drop__avg,2.30999999999999990605605015847601180212222971022129058837890625E-7
|
||||
ir__drop__worst,0.0001669999999999999935017258589908806243329308927059173583984375
|
||||
design__xor_difference__count,0
|
||||
magic__drc_error__count,0
|
||||
klayout__drc_error__count,0
|
||||
magic__illegal_overlap__count,0
|
||||
design__lvs_device_difference__count,0
|
||||
design__lvs_net_difference__count,0
|
||||
design__lvs_property_fail__count,0
|
||||
design__lvs_error__count,0
|
||||
design__lvs_unmatched_device__count,0
|
||||
design__lvs_unmatched_net__count,0
|
||||
design__lvs_unmatched_pin__count,0
|
||||
|
Reference in New Issue
Block a user