Initial commit

This commit is contained in:
2026-02-23 20:42:11 -07:00
committed by GitHub
commit 2ba96a115d
462 changed files with 9166588 additions and 0 deletions

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===========================================================================
report_checks -unconstrained
===========================================================================
======================= max_ff_n40C_1v95 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: _305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 v input external delay
2 0.004856 0.000000 0.000000 18.070000 v wb_rst_i (in)
wb_rst_i (net)
0.000181 0.000091 18.070089 v input37/A (sky130_fd_sc_hd__buf_4)
3 0.110424 0.098336 0.125718 18.195808 v input37/X (sky130_fd_sc_hd__buf_4)
net37 (net)
0.135287 0.046743 18.242552 v _153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005730 0.075903 0.116115 18.358665 ^ _153_/Y (sky130_fd_sc_hd__a21oi_4)
_039_ (net)
0.075904 0.000320 18.358986 ^ hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.005266 0.053893 0.393303 18.752289 ^ hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
net324 (net)
0.053893 0.000369 18.752659 ^ hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.064470 0.481229 0.688093 19.440752 ^ hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
net282 (net)
0.481325 0.006683 19.447435 ^ hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.045561 0.343535 0.616277 20.063711 ^ hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
net325 (net)
0.343539 0.001823 20.065535 ^ _160_/A (sky130_fd_sc_hd__nand2_2)
2 0.016516 0.100649 0.071001 20.136536 v _160_/Y (sky130_fd_sc_hd__nand2_2)
_044_ (net)
0.100708 0.001855 20.138390 v hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.049854 0.178902 0.528459 20.666849 v hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
net326 (net)
0.179036 0.004416 20.671265 v fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.138553 0.086504 0.171376 20.842640 v fanout124/X (sky130_fd_sc_hd__buf_6)
net124 (net)
0.086895 0.005862 20.848503 v _161_/A (sky130_fd_sc_hd__inv_2)
2 0.007811 0.040688 0.060034 20.908535 ^ _161_/Y (sky130_fd_sc_hd__inv_2)
_000_ (net)
0.040691 0.000369 20.908905 ^ _233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002588 0.036818 0.083903 20.992807 ^ _233_/X (sky130_fd_sc_hd__a32o_1)
_009_ (net)
0.036818 0.000108 20.992916 ^ hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002569 0.035881 0.370500 21.363417 ^ hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
net431 (net)
0.035881 0.000187 21.363604 ^ hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.003126 0.039863 0.373847 21.737450 ^ hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
net315 (net)
0.039863 0.000234 21.737684 ^ hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002185 0.033721 0.368708 22.106392 ^ hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
net432 (net)
0.033721 0.000158 22.106550 ^ _305_/D (sky130_fd_sc_hd__dfxtp_4)
22.106550 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.032763 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.618803 0.004402 29.654400 ^ wire3/A (sky130_fd_sc_hd__buf_4)
3 0.049820 0.112641 0.158005 29.812407 ^ wire3/X (sky130_fd_sc_hd__buf_4)
net274 (net)
0.114199 0.010509 29.822914 ^ wire2/A (sky130_fd_sc_hd__buf_6)
3 0.112546 0.170016 0.169734 29.992649 ^ wire2/X (sky130_fd_sc_hd__buf_6)
net273 (net)
0.171907 0.014463 30.007113 ^ _155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.055033 0.362209 0.330900 30.338013 ^ _155_/X (sky130_fd_sc_hd__mux2_1)
clk (net)
0.362317 0.005212 30.343224 ^ wire1/A (sky130_fd_sc_hd__buf_4)
3 0.051820 0.114516 0.160306 30.503529 ^ wire1/X (sky130_fd_sc_hd__buf_4)
net272 (net)
0.116068 0.010619 30.514149 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.097281 0.088029 0.147494 30.661642 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_0_clk (net)
0.089284 0.008317 30.669960 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.068737 0.066371 0.123642 30.793602 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_2_2__leaf_clk (net)
0.071567 0.014406 30.808008 ^ _305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 30.558006 clock uncertainty
0.000000 30.558006 clock reconvergence pessimism
-0.030632 30.527376 library setup time
30.527376 data required time
---------------------------------------------------------------------------------------------
30.527376 data required time
-22.106550 data arrival time
---------------------------------------------------------------------------------------------
8.420825 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
fanout124/X 16 33 -17 (VIOLATED)
fanout125/X 16 33 -17 (VIOLATED)
_159_/Y 16 29 -13 (VIOLATED)
_156_/X 16 27 -11 (VIOLATED)
_195_/X 16 23 -7 (VIOLATED)
_182_/X 16 21 -5 (VIOLATED)
clkbuf_2_2__f_clk/X 16 21 -5 (VIOLATED)
_176_/Y 16 19 -3 (VIOLATED)
_297_/Q 16 19 -3 (VIOLATED)
clkbuf_2_1__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_3__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_0__f_clk/X 16 17 (VIOLATED)
hold140/X 16 17 (VIOLATED)
wire4/X 16 17 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 420 unannotated drivers.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
la_data_in[0]
la_data_in[100]
la_data_in[101]
la_data_in[102]
la_data_in[103]
la_data_in[104]
la_data_in[105]
la_data_in[106]
la_data_in[107]
la_data_in[108]
la_data_in[109]
la_data_in[10]
la_data_in[110]
la_data_in[111]
la_data_in[112]
la_data_in[113]
la_data_in[114]
la_data_in[115]
la_data_in[116]
la_data_in[117]
la_data_in[118]
la_data_in[119]
la_data_in[11]
la_data_in[120]
la_data_in[121]
la_data_in[122]
la_data_in[123]
la_data_in[124]
la_data_in[125]
la_data_in[126]
la_data_in[127]
la_data_in[12]
la_data_in[13]
la_data_in[14]
la_data_in[15]
la_data_in[16]
la_data_in[17]
la_data_in[18]
la_data_in[19]
la_data_in[1]
la_data_in[20]
la_data_in[21]
la_data_in[22]
la_data_in[23]
la_data_in[24]
la_data_in[25]
la_data_in[26]
la_data_in[27]
la_data_in[28]
la_data_in[29]
la_data_in[2]
la_data_in[30]
la_data_in[31]
la_data_in[32]
la_data_in[33]
la_data_in[34]
la_data_in[35]
la_data_in[36]
la_data_in[37]
la_data_in[38]
la_data_in[39]
la_data_in[3]
la_data_in[40]
la_data_in[41]
la_data_in[42]
la_data_in[43]
la_data_in[44]
la_data_in[45]
la_data_in[46]
la_data_in[47]
la_data_in[4]
la_data_in[5]
la_data_in[66]
la_data_in[67]
la_data_in[68]
la_data_in[69]
la_data_in[6]
la_data_in[70]
la_data_in[71]
la_data_in[72]
la_data_in[73]
la_data_in[74]
la_data_in[75]
la_data_in[76]
la_data_in[77]
la_data_in[78]
la_data_in[79]
la_data_in[7]
la_data_in[80]
la_data_in[81]
la_data_in[82]
la_data_in[83]
la_data_in[84]
la_data_in[85]
la_data_in[86]
la_data_in[87]
la_data_in[88]
la_data_in[89]
la_data_in[8]
la_data_in[90]
la_data_in[91]
la_data_in[92]
la_data_in[93]
la_data_in[94]
la_data_in[95]
la_data_in[96]
la_data_in[97]
la_data_in[98]
la_data_in[99]
la_data_in[9]
la_oenb[0]
la_oenb[100]
la_oenb[101]
la_oenb[102]
la_oenb[103]
la_oenb[104]
la_oenb[105]
la_oenb[106]
la_oenb[107]
la_oenb[108]
la_oenb[109]
la_oenb[10]
la_oenb[110]
la_oenb[111]
la_oenb[112]
la_oenb[113]
la_oenb[114]
la_oenb[115]
la_oenb[116]
la_oenb[117]
la_oenb[118]
la_oenb[119]
la_oenb[11]
la_oenb[120]
la_oenb[121]
la_oenb[122]
la_oenb[123]
la_oenb[124]
la_oenb[125]
la_oenb[126]
la_oenb[127]
la_oenb[12]
la_oenb[13]
la_oenb[14]
la_oenb[15]
la_oenb[16]
la_oenb[17]
la_oenb[18]
la_oenb[19]
la_oenb[1]
la_oenb[20]
la_oenb[21]
la_oenb[22]
la_oenb[23]
la_oenb[24]
la_oenb[25]
la_oenb[26]
la_oenb[27]
la_oenb[28]
la_oenb[29]
la_oenb[2]
la_oenb[30]
la_oenb[31]
la_oenb[32]
la_oenb[33]
la_oenb[34]
la_oenb[35]
la_oenb[36]
la_oenb[37]
la_oenb[38]
la_oenb[39]
la_oenb[3]
la_oenb[40]
la_oenb[41]
la_oenb[42]
la_oenb[43]
la_oenb[44]
la_oenb[45]
la_oenb[46]
la_oenb[47]
la_oenb[4]
la_oenb[5]
la_oenb[66]
la_oenb[67]
la_oenb[68]
la_oenb[69]
la_oenb[6]
la_oenb[70]
la_oenb[71]
la_oenb[72]
la_oenb[73]
la_oenb[74]
la_oenb[75]
la_oenb[76]
la_oenb[77]
la_oenb[78]
la_oenb[79]
la_oenb[7]
la_oenb[80]
la_oenb[81]
la_oenb[82]
la_oenb[83]
la_oenb[84]
la_oenb[85]
la_oenb[86]
la_oenb[87]
la_oenb[88]
la_oenb[89]
la_oenb[8]
la_oenb[90]
la_oenb[91]
la_oenb[92]
la_oenb[93]
la_oenb[94]
la_oenb[95]
la_oenb[96]
la_oenb[97]
la_oenb[98]
la_oenb[99]
la_oenb[9]
wbs_adr_i[0]
wbs_adr_i[10]
wbs_adr_i[11]
wbs_adr_i[12]
wbs_adr_i[13]
wbs_adr_i[14]
wbs_adr_i[15]
wbs_adr_i[16]
wbs_adr_i[17]
wbs_adr_i[18]
wbs_adr_i[19]
wbs_adr_i[1]
wbs_adr_i[20]
wbs_adr_i[21]
wbs_adr_i[22]
wbs_adr_i[23]
wbs_adr_i[24]
wbs_adr_i[25]
wbs_adr_i[26]
wbs_adr_i[27]
wbs_adr_i[28]
wbs_adr_i[29]
wbs_adr_i[2]
wbs_adr_i[30]
wbs_adr_i[31]
wbs_adr_i[3]
wbs_adr_i[4]
wbs_adr_i[5]
wbs_adr_i[6]
wbs_adr_i[7]
wbs_adr_i[8]
wbs_adr_i[9]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_sel_i[2]
wbs_sel_i[3]
clkload0/X
clkload1/X
clkload2/X
user_proj_example_141/HI
user_proj_example_142/HI
user_proj_example_143/HI
user_proj_example_144/HI
user_proj_example_145/HI
user_proj_example_146/HI
user_proj_example_147/HI
user_proj_example_148/HI
user_proj_example_149/HI
user_proj_example_150/HI
user_proj_example_151/HI
user_proj_example_152/HI
user_proj_example_153/HI
user_proj_example_154/HI
user_proj_example_155/HI
user_proj_example_156/HI
user_proj_example_157/HI
user_proj_example_158/HI
user_proj_example_159/HI
user_proj_example_160/HI
user_proj_example_161/HI
user_proj_example_162/HI
user_proj_example_163/HI
user_proj_example_164/HI
user_proj_example_165/HI
user_proj_example_166/HI
user_proj_example_167/HI
user_proj_example_168/HI
user_proj_example_169/HI
user_proj_example_170/HI
user_proj_example_171/HI
user_proj_example_172/HI
user_proj_example_173/HI
user_proj_example_174/HI
user_proj_example_175/HI
user_proj_example_176/HI
user_proj_example_177/HI
user_proj_example_178/HI
user_proj_example_179/HI
user_proj_example_180/HI
user_proj_example_181/HI
user_proj_example_182/HI
user_proj_example_183/HI
user_proj_example_184/HI
user_proj_example_185/HI
user_proj_example_186/HI
user_proj_example_187/HI
user_proj_example_188/HI
user_proj_example_189/HI
user_proj_example_190/HI
user_proj_example_191/HI
user_proj_example_192/HI
user_proj_example_193/HI
user_proj_example_194/HI
user_proj_example_195/HI
user_proj_example_196/HI
user_proj_example_197/HI
user_proj_example_198/HI
user_proj_example_199/HI
user_proj_example_200/HI
user_proj_example_201/HI
user_proj_example_202/HI
user_proj_example_203/HI
user_proj_example_204/HI
user_proj_example_205/HI
user_proj_example_206/HI
user_proj_example_207/HI
user_proj_example_208/HI
user_proj_example_209/HI
user_proj_example_210/HI
user_proj_example_211/HI
user_proj_example_212/HI
user_proj_example_213/HI
user_proj_example_214/HI
user_proj_example_215/HI
user_proj_example_216/HI
user_proj_example_217/HI
user_proj_example_218/HI
user_proj_example_219/HI
user_proj_example_220/HI
user_proj_example_221/HI
user_proj_example_222/HI
user_proj_example_223/HI
user_proj_example_224/HI
user_proj_example_225/HI
user_proj_example_226/HI
user_proj_example_227/HI
user_proj_example_228/HI
user_proj_example_229/HI
user_proj_example_230/HI
user_proj_example_231/HI
user_proj_example_232/HI
user_proj_example_233/HI
user_proj_example_234/HI
user_proj_example_235/HI
user_proj_example_236/HI
user_proj_example_237/HI
user_proj_example_238/HI
user_proj_example_239/HI
user_proj_example_240/HI
user_proj_example_241/HI
user_proj_example_242/HI
user_proj_example_243/HI
user_proj_example_244/HI
user_proj_example_245/HI
user_proj_example_246/HI
user_proj_example_247/HI
user_proj_example_248/HI
user_proj_example_249/HI
user_proj_example_250/HI
user_proj_example_251/HI
user_proj_example_252/HI
user_proj_example_253/HI
user_proj_example_254/HI
user_proj_example_255/HI
user_proj_example_256/HI
user_proj_example_257/HI
user_proj_example_258/HI
user_proj_example_259/HI
user_proj_example_260/HI
user_proj_example_261/HI
user_proj_example_262/HI
user_proj_example_263/HI
user_proj_example_264/HI
user_proj_example_265/HI
user_proj_example_266/HI
user_proj_example_267/HI
user_proj_example_268/HI
user_proj_example_269/HI
user_proj_example_270/HI
user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 14
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 16 input ports missing set_input_delay.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
Warning: There are 163 unconstrained endpoints.
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[1]
io_oeb[2]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[1]
io_out[2]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
irq[0]
irq[1]
irq[2]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

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Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
5.793144 network latency _328_/CLK
8.802826 network latency _305_/CLK
---------------
10.443145 14.372827 latency
3.929682 skew
rise -> fall
min max
4.650000 5.570000 source latency
5.886471 network latency _328_/CLK
8.789217 network latency _305_/CLK
---------------
10.536470 14.359217 latency
3.822746 skew
fall -> fall
min max
4.650000 5.570000 source latency
5.926150 network latency _328_/CLK
6.861967 network latency _305_/CLK
---------------
10.576150 12.431967 latency
1.855817 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 3.67 fmax = 272.16

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===========================================================================
report_power
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 4.245963e-05 4.360105e-05 7.394261e-10 8.606142e-05 13.8%
Combinational 1.185844e-04 3.225572e-04 1.315145e-08 4.411547e-04 70.6%
Clock 3.455588e-05 6.339366e-05 5.304953e-09 9.795484e-05 15.7%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.955999e-04 4.295520e-04 1.919599e-08 6.251711e-04 100.0%
31.3% 68.7% 0.0%

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===========================================================================
Clock Skew (Setup)
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
Clock clk
8.802711 source latency _296_/CLK ^
-5.793144 target latency _328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.259567 setup skew

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===========================================================================
Clock Skew (Hold)
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
Clock clk
5.796201 source latency _306_/CLK ^
-6.727007 target latency _312_/CLK ^
-0.250000 clock uncertainty
-0.920002 CRPR
--------------
-2.100808 hold skew

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===========================================================================
Total Negative Slack (Setup)
============================================================================
max_ff_n40C_1v95: 0.0

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===========================================================================
Total Negative Slack (Hold)
============================================================================
max_ff_n40C_1v95: 0.0

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===========================================================================
Violator List
============================================================================

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===========================================================================
Worst Negative Slack (Setup)
============================================================================
max_ff_n40C_1v95: 0.0

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===========================================================================
Worst Negative Slack (Hold)
============================================================================
max_ff_n40C_1v95: 0

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@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
max_ff_n40C_1v95: 8.420825164404606

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===========================================================================
Worst Slack (Hold)
============================================================================
max_ff_n40C_1v95: 0.24338487469856057

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===========================================================================
report_checks -unconstrained
===========================================================================
======================= max_ss_100C_1v60 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: _305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 ^ input external delay
2 0.005301 0.000000 0.000000 18.070000 ^ wb_rst_i (in)
wb_rst_i (net)
0.000198 0.000099 18.070099 ^ input37/A (sky130_fd_sc_hd__buf_4)
3 0.111563 0.491044 0.452783 18.522882 ^ input37/X (sky130_fd_sc_hd__buf_4)
net37 (net)
0.499346 0.051172 18.574053 ^ _153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005400 0.118398 0.224244 18.798296 v _153_/Y (sky130_fd_sc_hd__a21oi_4)
_039_ (net)
0.118399 0.000288 18.798584 v hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004936 0.128301 1.179544 19.978128 v hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
net324 (net)
0.128301 0.000338 19.978466 v hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.063834 0.608758 1.639434 21.617899 v hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
net282 (net)
0.608824 0.006569 21.624468 v hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.045452 0.455615 1.756908 23.381376 v hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
net325 (net)
0.455615 0.001808 23.383184 v _160_/A (sky130_fd_sc_hd__nand2_2)
2 0.016709 0.203175 0.329706 23.712891 ^ _160_/Y (sky130_fd_sc_hd__nand2_2)
_044_ (net)
0.203190 0.001879 23.714769 ^ hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.050872 0.768606 1.615794 25.330563 ^ hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
net326 (net)
0.768623 0.004578 25.335140 ^ fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.141612 0.447056 0.662691 25.997831 ^ fanout124/X (sky130_fd_sc_hd__buf_6)
net124 (net)
0.447163 0.006048 26.003881 ^ _161_/A (sky130_fd_sc_hd__inv_2)
2 0.007357 0.099004 0.181235 26.185116 v _161_/Y (sky130_fd_sc_hd__inv_2)
_000_ (net)
0.099004 0.000346 26.185461 v _233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002258 0.066735 0.438190 26.623652 v _233_/X (sky130_fd_sc_hd__a32o_1)
_009_ (net)
0.066735 0.000092 26.623743 v hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002239 0.101244 1.112467 27.736210 v hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
net431 (net)
0.101244 0.000160 27.736370 v hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002796 0.105541 1.137940 28.874310 v hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
net315 (net)
0.105541 0.000208 28.874517 v hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.001921 0.098113 1.125233 29.999750 v hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
net432 (net)
0.098113 0.000139 29.999889 v _305_/D (sky130_fd_sc_hd__dfxtp_4)
29.999889 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.032914 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.618869 0.004436 29.654434 ^ wire3/A (sky130_fd_sc_hd__buf_4)
3 0.050133 0.234613 0.554135 30.208569 ^ wire3/X (sky130_fd_sc_hd__buf_4)
net274 (net)
0.235489 0.010623 30.219193 ^ wire2/A (sky130_fd_sc_hd__buf_6)
3 0.112773 0.356296 0.457192 30.676384 ^ wire2/X (sky130_fd_sc_hd__buf_6)
net273 (net)
0.357179 0.014580 30.690964 ^ _155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.055386 0.769394 0.863743 31.554707 ^ _155_/X (sky130_fd_sc_hd__mux2_1)
clk (net)
0.769420 0.005244 31.559950 ^ wire1/A (sky130_fd_sc_hd__buf_4)
3 0.052155 0.244788 0.600860 32.160809 ^ wire1/X (sky130_fd_sc_hd__buf_4)
net272 (net)
0.245654 0.010747 32.171558 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.098015 0.174219 0.388955 32.560513 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_0_clk (net)
0.174993 0.008434 32.568947 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.068929 0.133024 0.325134 32.894081 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_2_2__leaf_clk (net)
0.135672 0.014722 32.908802 ^ _305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 32.658802 clock uncertainty
0.000000 32.658802 clock reconvergence pessimism
-0.267000 32.391800 library setup time
32.391800 data required time
---------------------------------------------------------------------------------------------
32.391800 data required time
-29.999889 data arrival time
---------------------------------------------------------------------------------------------
2.391911 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------------------
_152_/B 1.000000 1.581131 -0.581131 (VIOLATED)
ANTENNA__152__B/DIODE 1.000000 1.581118 -0.581119 (VIOLATED)
ANTENNA_hold48_X/DIODE 1.000000 1.578318 -0.578318 (VIOLATED)
hold48/X 1.000000 1.578304 -0.578304 (VIOLATED)
ANTENNA__206__B1/DIODE 1.000000 1.441218 -0.441218 (VIOLATED)
_206_/B1 1.000000 1.441218 -0.441218 (VIOLATED)
ANTENNA_hold133_X/DIODE 1.000000 1.441158 -0.441158 (VIOLATED)
hold133/X 1.000000 1.441158 -0.441158 (VIOLATED)
_246_/A2 1.000000 1.391952 -0.391952 (VIOLATED)
ANTENNA__246__A2/DIODE 1.000000 1.391372 -0.391372 (VIOLATED)
ANTENNA_hold11_X/DIODE 1.000000 1.390723 -0.390723 (VIOLATED)
hold11/X 1.000000 1.390723 -0.390723 (VIOLATED)
_264_/B 1.000000 1.294601 -0.294601 (VIOLATED)
ANTENNA__264__B/DIODE 1.000000 1.294554 -0.294553 (VIOLATED)
_269_/B 1.000000 1.294549 -0.294549 (VIOLATED)
ANTENNA__269__B/DIODE 1.000000 1.294509 -0.294509 (VIOLATED)
_252_/B 1.000000 1.294377 -0.294377 (VIOLATED)
ANTENNA__252__B/DIODE 1.000000 1.294299 -0.294299 (VIOLATED)
ANTENNA__237__B/DIODE 1.000000 1.293545 -0.293545 (VIOLATED)
_237_/B 1.000000 1.293094 -0.293094 (VIOLATED)
_215_/B 1.000000 1.292107 -0.292107 (VIOLATED)
ANTENNA__215__B/DIODE 1.000000 1.292031 -0.292031 (VIOLATED)
_169_/B1 1.000000 1.291392 -0.291392 (VIOLATED)
ANTENNA__169__B1/DIODE 1.000000 1.291230 -0.291230 (VIOLATED)
ANTENNA__168__B1/DIODE 1.000000 1.290756 -0.290756 (VIOLATED)
_168_/B1 1.000000 1.290397 -0.290397 (VIOLATED)
_198_/B 1.000000 1.289137 -0.289137 (VIOLATED)
ANTENNA__198__B/DIODE 1.000000 1.288439 -0.288438 (VIOLATED)
_190_/B 1.000000 1.287292 -0.287292 (VIOLATED)
ANTENNA__190__B/DIODE 1.000000 1.287234 -0.287234 (VIOLATED)
_164_/A2 1.000000 1.286866 -0.286866 (VIOLATED)
_163_/A2 1.000000 1.286865 -0.286865 (VIOLATED)
ANTENNA__163__A2/DIODE 1.000000 1.286863 -0.286863 (VIOLATED)
ANTENNA__164__A2/DIODE 1.000000 1.286851 -0.286851 (VIOLATED)
_224_/A_N 1.000000 1.286807 -0.286807 (VIOLATED)
ANTENNA__224__A_N/DIODE 1.000000 1.286802 -0.286802 (VIOLATED)
ANTENNA_hold138_X/DIODE 1.000000 1.286354 -0.286354 (VIOLATED)
hold138/X 1.000000 1.286354 -0.286354 (VIOLATED)
_173_/B 1.000000 1.243996 -0.243996 (VIOLATED)
ANTENNA__173__B/DIODE 1.000000 1.243818 -0.243818 (VIOLATED)
_164_/B1 1.000000 1.242228 -0.242228 (VIOLATED)
ANTENNA__164__B1/DIODE 1.000000 1.240808 -0.240808 (VIOLATED)
_163_/B1 1.000000 1.239655 -0.239655 (VIOLATED)
ANTENNA__163__B1/DIODE 1.000000 1.239652 -0.239652 (VIOLATED)
_170_/B 1.000000 1.239646 -0.239646 (VIOLATED)
ANTENNA__170__B/DIODE 1.000000 1.238607 -0.238607 (VIOLATED)
_253_/B1 1.000000 1.224410 -0.224410 (VIOLATED)
ANTENNA__253__B1/DIODE 1.000000 1.224408 -0.224408 (VIOLATED)
ANTENNA_hold81_X/DIODE 1.000000 1.224358 -0.224358 (VIOLATED)
hold81/X 1.000000 1.224358 -0.224358 (VIOLATED)
ANTENNA__156__X/DIODE 1.000000 1.223390 -0.223390 (VIOLATED)
_156_/X 1.000000 1.223235 -0.223236 (VIOLATED)
output77/A 1.000000 1.187443 -0.187444 (VIOLATED)
ANTENNA_output77_A/DIODE 1.000000 1.187355 -0.187355 (VIOLATED)
wire134/A 1.000000 1.183137 -0.183137 (VIOLATED)
ANTENNA_wire134_A/DIODE 1.000000 1.183046 -0.183046 (VIOLATED)
_285_/A0 1.000000 1.176307 -0.176307 (VIOLATED)
ANTENNA__285__A0/DIODE 1.000000 1.176299 -0.176299 (VIOLATED)
ANTENNA__191__B1/DIODE 1.000000 1.172638 -0.172638 (VIOLATED)
_191_/B1 1.000000 1.172638 -0.172638 (VIOLATED)
_221_/B 1.000000 1.172495 -0.172495 (VIOLATED)
ANTENNA__221__B/DIODE 1.000000 1.172454 -0.172454 (VIOLATED)
hold129/A 1.000000 1.171979 -0.171979 (VIOLATED)
ANTENNA_hold129_A/DIODE 1.000000 1.171965 -0.171965 (VIOLATED)
ANTENNA__209__B1/DIODE 1.000000 1.171660 -0.171660 (VIOLATED)
_209_/B1 1.000000 1.171651 -0.171651 (VIOLATED)
_208_/B 1.000000 1.171489 -0.171489 (VIOLATED)
ANTENNA__208__B/DIODE 1.000000 1.171473 -0.171473 (VIOLATED)
ANTENNA__302__Q/DIODE 1.000000 1.171368 -0.171368 (VIOLATED)
_302_/Q 1.000000 1.171263 -0.171262 (VIOLATED)
ANTENNA_hold61_X/DIODE 1.000000 1.171025 -0.171025 (VIOLATED)
hold61/X 1.000000 1.171025 -0.171025 (VIOLATED)
_265_/B1 1.000000 1.170157 -0.170157 (VIOLATED)
ANTENNA__265__B1/DIODE 1.000000 1.170155 -0.170155 (VIOLATED)
ANTENNA_hold66_X/DIODE 1.000000 1.170109 -0.170109 (VIOLATED)
hold66/X 1.000000 1.170109 -0.170109 (VIOLATED)
_467_/A 1.000000 1.168521 -0.168521 (VIOLATED)
ANTENNA__467__A/DIODE 1.000000 1.168468 -0.168467 (VIOLATED)
_466_/A 1.000000 1.167774 -0.167774 (VIOLATED)
ANTENNA__466__A/DIODE 1.000000 1.167723 -0.167723 (VIOLATED)
wire136/A 1.000000 1.160894 -0.160894 (VIOLATED)
ANTENNA_wire136_A/DIODE 1.000000 1.160856 -0.160856 (VIOLATED)
_291_/A0 1.000000 1.160227 -0.160227 (VIOLATED)
ANTENNA__291__A0/DIODE 1.000000 1.160217 -0.160217 (VIOLATED)
_465_/A 1.000000 1.160097 -0.160097 (VIOLATED)
ANTENNA__465__A/DIODE 1.000000 1.160046 -0.160046 (VIOLATED)
_250_/B1 1.000000 1.159148 -0.159148 (VIOLATED)
_248_/D 1.000000 1.159145 -0.159145 (VIOLATED)
ANTENNA__248__D/DIODE 1.000000 1.159145 -0.159145 (VIOLATED)
ANTENNA__250__B1/DIODE 1.000000 1.159145 -0.159145 (VIOLATED)
hold125/A 1.000000 1.159077 -0.159077 (VIOLATED)
ANTENNA_hold125_A/DIODE 1.000000 1.159077 -0.159077 (VIOLATED)
ANTENNA__308__Q/DIODE 1.000000 1.159074 -0.159074 (VIOLATED)
_308_/Q 1.000000 1.159032 -0.159032 (VIOLATED)
_283_/A0 1.000000 1.157434 -0.157434 (VIOLATED)
ANTENNA__283__A0/DIODE 1.000000 1.157429 -0.157429 (VIOLATED)
_195_/D 1.000000 1.156807 -0.156807 (VIOLATED)
ANTENNA__195__D/DIODE 1.000000 1.156806 -0.156806 (VIOLATED)
hold127/A 1.000000 1.156562 -0.156562 (VIOLATED)
ANTENNA_hold127_A/DIODE 1.000000 1.156529 -0.156529 (VIOLATED)
ANTENNA__300__Q/DIODE 1.000000 1.156351 -0.156351 (VIOLATED)
_196_/B1 1.000000 1.156340 -0.156340 (VIOLATED)
ANTENNA__196__B1/DIODE 1.000000 1.156339 -0.156339 (VIOLATED)
_300_/Q 1.000000 1.156256 -0.156256 (VIOLATED)
_216_/A1 1.000000 1.148196 -0.148196 (VIOLATED)
_199_/A1 1.000000 1.148192 -0.148192 (VIOLATED)
ANTENNA__199__A1/DIODE 1.000000 1.148190 -0.148190 (VIOLATED)
ANTENNA__216__A1/DIODE 1.000000 1.148187 -0.148187 (VIOLATED)
_270_/A1 1.000000 1.148159 -0.148159 (VIOLATED)
ANTENNA__270__A1/DIODE 1.000000 1.148157 -0.148157 (VIOLATED)
_187_/A1 1.000000 1.148136 -0.148136 (VIOLATED)
ANTENNA__187__A1/DIODE 1.000000 1.148135 -0.148135 (VIOLATED)
_265_/A1 1.000000 1.148133 -0.148133 (VIOLATED)
ANTENNA__191__A1/DIODE 1.000000 1.148132 -0.148132 (VIOLATED)
ANTENNA__265__A1/DIODE 1.000000 1.148130 -0.148130 (VIOLATED)
_191_/A1 1.000000 1.148129 -0.148130 (VIOLATED)
_226_/A1 1.000000 1.148126 -0.148126 (VIOLATED)
ANTENNA__226__A1/DIODE 1.000000 1.148123 -0.148123 (VIOLATED)
ANTENNA_hold140_X/DIODE 1.000000 1.148089 -0.148089 (VIOLATED)
ANTENNA__253__A1/DIODE 1.000000 1.148087 -0.148087 (VIOLATED)
_253_/A1 1.000000 1.148087 -0.148087 (VIOLATED)
hold140/X 1.000000 1.148087 -0.148087 (VIOLATED)
_464_/A 1.000000 1.144495 -0.144495 (VIOLATED)
ANTENNA__464__A/DIODE 1.000000 1.144444 -0.144443 (VIOLATED)
_463_/A 1.000000 1.120713 -0.120713 (VIOLATED)
ANTENNA__463__A/DIODE 1.000000 1.120667 -0.120667 (VIOLATED)
_238_/A2 1.000000 1.097788 -0.097788 (VIOLATED)
ANTENNA__238__A2/DIODE 1.000000 1.097786 -0.097786 (VIOLATED)
ANTENNA_hold76_X/DIODE 1.000000 1.097744 -0.097744 (VIOLATED)
hold76/X 1.000000 1.097744 -0.097744 (VIOLATED)
_211_/A 1.000000 1.097005 -0.097005 (VIOLATED)
ANTENNA__211__A/DIODE 1.000000 1.097004 -0.097004 (VIOLATED)
ANTENNA_hold2_X/DIODE 1.000000 1.096972 -0.096972 (VIOLATED)
hold2/X 1.000000 1.096972 -0.096972 (VIOLATED)
_462_/A 1.000000 1.089118 -0.089118 (VIOLATED)
ANTENNA__462__A/DIODE 1.000000 1.089066 -0.089066 (VIOLATED)
wire135/A 1.000000 1.081332 -0.081332 (VIOLATED)
ANTENNA_wire135_A/DIODE 1.000000 1.081278 -0.081278 (VIOLATED)
_275_/B2 1.000000 1.080290 -0.080290 (VIOLATED)
ANTENNA__275__B2/DIODE 1.000000 1.080288 -0.080288 (VIOLATED)
ANTENNA_hold15_X/DIODE 1.000000 1.078915 -0.078915 (VIOLATED)
hold15/X 1.000000 1.078915 -0.078915 (VIOLATED)
_284_/A0 1.000000 1.068883 -0.068883 (VIOLATED)
ANTENNA__284__A0/DIODE 1.000000 1.068875 -0.068875 (VIOLATED)
_208_/A 1.000000 1.068768 -0.068768 (VIOLATED)
_209_/A1 1.000000 1.068331 -0.068331 (VIOLATED)
ANTENNA__208__A/DIODE 1.000000 1.068285 -0.068285 (VIOLATED)
ANTENNA__209__A1/DIODE 1.000000 1.068268 -0.068268 (VIOLATED)
_221_/A 1.000000 1.068004 -0.068004 (VIOLATED)
ANTENNA__221__A/DIODE 1.000000 1.068004 -0.068003 (VIOLATED)
_203_/A 1.000000 1.067785 -0.067785 (VIOLATED)
ANTENNA__203__A/DIODE 1.000000 1.067762 -0.067762 (VIOLATED)
hold128/A 1.000000 1.067589 -0.067589 (VIOLATED)
ANTENNA__301__Q/DIODE 1.000000 1.067589 -0.067589 (VIOLATED)
ANTENNA_hold128_A/DIODE 1.000000 1.067588 -0.067588 (VIOLATED)
_301_/Q 1.000000 1.067503 -0.067503 (VIOLATED)
output78/A 1.000000 1.066017 -0.066017 (VIOLATED)
ANTENNA_output78_A/DIODE 1.000000 1.065946 -0.065945 (VIOLATED)
_461_/A 1.000000 1.050228 -0.050228 (VIOLATED)
ANTENNA__461__A/DIODE 1.000000 1.049922 -0.049922 (VIOLATED)
ANTENNA__258__C1/DIODE 1.000000 1.049824 -0.049824 (VIOLATED)
_258_/C1 1.000000 1.049823 -0.049823 (VIOLATED)
_292_/A0 1.000000 1.049651 -0.049651 (VIOLATED)
ANTENNA__292__A0/DIODE 1.000000 1.049647 -0.049647 (VIOLATED)
ANTENNA_hold21_X/DIODE 1.000000 1.049210 -0.049210 (VIOLATED)
hold21/X 1.000000 1.049210 -0.049210 (VIOLATED)
_260_/A 1.000000 1.048881 -0.048881 (VIOLATED)
_262_/A1 1.000000 1.048881 -0.048881 (VIOLATED)
ANTENNA__260__A/DIODE 1.000000 1.048881 -0.048881 (VIOLATED)
ANTENNA__262__A1/DIODE 1.000000 1.048877 -0.048877 (VIOLATED)
hold126/A 1.000000 1.048867 -0.048867 (VIOLATED)
_256_/A 1.000000 1.048863 -0.048863 (VIOLATED)
ANTENNA_hold126_A/DIODE 1.000000 1.048863 -0.048863 (VIOLATED)
ANTENNA__256__A/DIODE 1.000000 1.048860 -0.048860 (VIOLATED)
ANTENNA__309__Q/DIODE 1.000000 1.048841 -0.048840 (VIOLATED)
_309_/Q 1.000000 1.048802 -0.048802 (VIOLATED)
_270_/B1 1.000000 1.047741 -0.047741 (VIOLATED)
ANTENNA__270__B1/DIODE 1.000000 1.047734 -0.047734 (VIOLATED)
ANTENNA_hold71_X/DIODE 1.000000 1.047081 -0.047081 (VIOLATED)
hold71/X 1.000000 1.047081 -0.047081 (VIOLATED)
output79/A 1.000000 1.038402 -0.038402 (VIOLATED)
ANTENNA_output79_A/DIODE 1.000000 1.038288 -0.038288 (VIOLATED)
_199_/B1 1.000000 1.033128 -0.033128 (VIOLATED)
ANTENNA__199__B1/DIODE 1.000000 1.033125 -0.033125 (VIOLATED)
ANTENNA_hold44_X/DIODE 1.000000 1.032860 -0.032860 (VIOLATED)
hold44/X 1.000000 1.032860 -0.032860 (VIOLATED)
_217_/A 1.000000 1.018557 -0.018557 (VIOLATED)
ANTENNA__217__A/DIODE 1.000000 1.018546 -0.018546 (VIOLATED)
ANTENNA_hold170_X/DIODE 1.000000 1.017920 -0.017920 (VIOLATED)
hold170/X 1.000000 1.017920 -0.017920 (VIOLATED)
ANTENNA__293__A0/DIODE 1.000000 1.014856 -0.014856 (VIOLATED)
_293_/A0 1.000000 1.013363 -0.013363 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
fanout124/X 16 33 -17 (VIOLATED)
fanout125/X 16 33 -17 (VIOLATED)
_159_/Y 16 29 -13 (VIOLATED)
_156_/X 16 27 -11 (VIOLATED)
_195_/X 16 23 -7 (VIOLATED)
_182_/X 16 21 -5 (VIOLATED)
clkbuf_2_2__f_clk/X 16 21 -5 (VIOLATED)
_176_/Y 16 19 -3 (VIOLATED)
_297_/Q 16 19 -3 (VIOLATED)
clkbuf_2_1__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_3__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_0__f_clk/X 16 17 (VIOLATED)
hold140/X 16 17 (VIOLATED)
wire4/X 16 17 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------------------
hold48/X 0.100718 0.106189 -0.005471 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 420 unannotated drivers.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
la_data_in[0]
la_data_in[100]
la_data_in[101]
la_data_in[102]
la_data_in[103]
la_data_in[104]
la_data_in[105]
la_data_in[106]
la_data_in[107]
la_data_in[108]
la_data_in[109]
la_data_in[10]
la_data_in[110]
la_data_in[111]
la_data_in[112]
la_data_in[113]
la_data_in[114]
la_data_in[115]
la_data_in[116]
la_data_in[117]
la_data_in[118]
la_data_in[119]
la_data_in[11]
la_data_in[120]
la_data_in[121]
la_data_in[122]
la_data_in[123]
la_data_in[124]
la_data_in[125]
la_data_in[126]
la_data_in[127]
la_data_in[12]
la_data_in[13]
la_data_in[14]
la_data_in[15]
la_data_in[16]
la_data_in[17]
la_data_in[18]
la_data_in[19]
la_data_in[1]
la_data_in[20]
la_data_in[21]
la_data_in[22]
la_data_in[23]
la_data_in[24]
la_data_in[25]
la_data_in[26]
la_data_in[27]
la_data_in[28]
la_data_in[29]
la_data_in[2]
la_data_in[30]
la_data_in[31]
la_data_in[32]
la_data_in[33]
la_data_in[34]
la_data_in[35]
la_data_in[36]
la_data_in[37]
la_data_in[38]
la_data_in[39]
la_data_in[3]
la_data_in[40]
la_data_in[41]
la_data_in[42]
la_data_in[43]
la_data_in[44]
la_data_in[45]
la_data_in[46]
la_data_in[47]
la_data_in[4]
la_data_in[5]
la_data_in[66]
la_data_in[67]
la_data_in[68]
la_data_in[69]
la_data_in[6]
la_data_in[70]
la_data_in[71]
la_data_in[72]
la_data_in[73]
la_data_in[74]
la_data_in[75]
la_data_in[76]
la_data_in[77]
la_data_in[78]
la_data_in[79]
la_data_in[7]
la_data_in[80]
la_data_in[81]
la_data_in[82]
la_data_in[83]
la_data_in[84]
la_data_in[85]
la_data_in[86]
la_data_in[87]
la_data_in[88]
la_data_in[89]
la_data_in[8]
la_data_in[90]
la_data_in[91]
la_data_in[92]
la_data_in[93]
la_data_in[94]
la_data_in[95]
la_data_in[96]
la_data_in[97]
la_data_in[98]
la_data_in[99]
la_data_in[9]
la_oenb[0]
la_oenb[100]
la_oenb[101]
la_oenb[102]
la_oenb[103]
la_oenb[104]
la_oenb[105]
la_oenb[106]
la_oenb[107]
la_oenb[108]
la_oenb[109]
la_oenb[10]
la_oenb[110]
la_oenb[111]
la_oenb[112]
la_oenb[113]
la_oenb[114]
la_oenb[115]
la_oenb[116]
la_oenb[117]
la_oenb[118]
la_oenb[119]
la_oenb[11]
la_oenb[120]
la_oenb[121]
la_oenb[122]
la_oenb[123]
la_oenb[124]
la_oenb[125]
la_oenb[126]
la_oenb[127]
la_oenb[12]
la_oenb[13]
la_oenb[14]
la_oenb[15]
la_oenb[16]
la_oenb[17]
la_oenb[18]
la_oenb[19]
la_oenb[1]
la_oenb[20]
la_oenb[21]
la_oenb[22]
la_oenb[23]
la_oenb[24]
la_oenb[25]
la_oenb[26]
la_oenb[27]
la_oenb[28]
la_oenb[29]
la_oenb[2]
la_oenb[30]
la_oenb[31]
la_oenb[32]
la_oenb[33]
la_oenb[34]
la_oenb[35]
la_oenb[36]
la_oenb[37]
la_oenb[38]
la_oenb[39]
la_oenb[3]
la_oenb[40]
la_oenb[41]
la_oenb[42]
la_oenb[43]
la_oenb[44]
la_oenb[45]
la_oenb[46]
la_oenb[47]
la_oenb[4]
la_oenb[5]
la_oenb[66]
la_oenb[67]
la_oenb[68]
la_oenb[69]
la_oenb[6]
la_oenb[70]
la_oenb[71]
la_oenb[72]
la_oenb[73]
la_oenb[74]
la_oenb[75]
la_oenb[76]
la_oenb[77]
la_oenb[78]
la_oenb[79]
la_oenb[7]
la_oenb[80]
la_oenb[81]
la_oenb[82]
la_oenb[83]
la_oenb[84]
la_oenb[85]
la_oenb[86]
la_oenb[87]
la_oenb[88]
la_oenb[89]
la_oenb[8]
la_oenb[90]
la_oenb[91]
la_oenb[92]
la_oenb[93]
la_oenb[94]
la_oenb[95]
la_oenb[96]
la_oenb[97]
la_oenb[98]
la_oenb[99]
la_oenb[9]
wbs_adr_i[0]
wbs_adr_i[10]
wbs_adr_i[11]
wbs_adr_i[12]
wbs_adr_i[13]
wbs_adr_i[14]
wbs_adr_i[15]
wbs_adr_i[16]
wbs_adr_i[17]
wbs_adr_i[18]
wbs_adr_i[19]
wbs_adr_i[1]
wbs_adr_i[20]
wbs_adr_i[21]
wbs_adr_i[22]
wbs_adr_i[23]
wbs_adr_i[24]
wbs_adr_i[25]
wbs_adr_i[26]
wbs_adr_i[27]
wbs_adr_i[28]
wbs_adr_i[29]
wbs_adr_i[2]
wbs_adr_i[30]
wbs_adr_i[31]
wbs_adr_i[3]
wbs_adr_i[4]
wbs_adr_i[5]
wbs_adr_i[6]
wbs_adr_i[7]
wbs_adr_i[8]
wbs_adr_i[9]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_sel_i[2]
wbs_sel_i[3]
clkload0/X
clkload1/X
clkload2/X
user_proj_example_141/HI
user_proj_example_142/HI
user_proj_example_143/HI
user_proj_example_144/HI
user_proj_example_145/HI
user_proj_example_146/HI
user_proj_example_147/HI
user_proj_example_148/HI
user_proj_example_149/HI
user_proj_example_150/HI
user_proj_example_151/HI
user_proj_example_152/HI
user_proj_example_153/HI
user_proj_example_154/HI
user_proj_example_155/HI
user_proj_example_156/HI
user_proj_example_157/HI
user_proj_example_158/HI
user_proj_example_159/HI
user_proj_example_160/HI
user_proj_example_161/HI
user_proj_example_162/HI
user_proj_example_163/HI
user_proj_example_164/HI
user_proj_example_165/HI
user_proj_example_166/HI
user_proj_example_167/HI
user_proj_example_168/HI
user_proj_example_169/HI
user_proj_example_170/HI
user_proj_example_171/HI
user_proj_example_172/HI
user_proj_example_173/HI
user_proj_example_174/HI
user_proj_example_175/HI
user_proj_example_176/HI
user_proj_example_177/HI
user_proj_example_178/HI
user_proj_example_179/HI
user_proj_example_180/HI
user_proj_example_181/HI
user_proj_example_182/HI
user_proj_example_183/HI
user_proj_example_184/HI
user_proj_example_185/HI
user_proj_example_186/HI
user_proj_example_187/HI
user_proj_example_188/HI
user_proj_example_189/HI
user_proj_example_190/HI
user_proj_example_191/HI
user_proj_example_192/HI
user_proj_example_193/HI
user_proj_example_194/HI
user_proj_example_195/HI
user_proj_example_196/HI
user_proj_example_197/HI
user_proj_example_198/HI
user_proj_example_199/HI
user_proj_example_200/HI
user_proj_example_201/HI
user_proj_example_202/HI
user_proj_example_203/HI
user_proj_example_204/HI
user_proj_example_205/HI
user_proj_example_206/HI
user_proj_example_207/HI
user_proj_example_208/HI
user_proj_example_209/HI
user_proj_example_210/HI
user_proj_example_211/HI
user_proj_example_212/HI
user_proj_example_213/HI
user_proj_example_214/HI
user_proj_example_215/HI
user_proj_example_216/HI
user_proj_example_217/HI
user_proj_example_218/HI
user_proj_example_219/HI
user_proj_example_220/HI
user_proj_example_221/HI
user_proj_example_222/HI
user_proj_example_223/HI
user_proj_example_224/HI
user_proj_example_225/HI
user_proj_example_226/HI
user_proj_example_227/HI
user_proj_example_228/HI
user_proj_example_229/HI
user_proj_example_230/HI
user_proj_example_231/HI
user_proj_example_232/HI
user_proj_example_233/HI
user_proj_example_234/HI
user_proj_example_235/HI
user_proj_example_236/HI
user_proj_example_237/HI
user_proj_example_238/HI
user_proj_example_239/HI
user_proj_example_240/HI
user_proj_example_241/HI
user_proj_example_242/HI
user_proj_example_243/HI
user_proj_example_244/HI
user_proj_example_245/HI
user_proj_example_246/HI
user_proj_example_247/HI
user_proj_example_248/HI
user_proj_example_249/HI
user_proj_example_250/HI
user_proj_example_251/HI
user_proj_example_252/HI
user_proj_example_253/HI
user_proj_example_254/HI
user_proj_example_255/HI
user_proj_example_256/HI
user_proj_example_257/HI
user_proj_example_258/HI
user_proj_example_259/HI
user_proj_example_260/HI
user_proj_example_261/HI
user_proj_example_262/HI
user_proj_example_263/HI
user_proj_example_264/HI
user_proj_example_265/HI
user_proj_example_266/HI
user_proj_example_267/HI
user_proj_example_268/HI
user_proj_example_269/HI
user_proj_example_270/HI
user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 192
max fanout violation count 14
max cap violation count 1
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 16 input ports missing set_input_delay.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
Warning: There are 163 unconstrained endpoints.
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[1]
io_oeb[2]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[1]
io_out[2]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
irq[0]
irq[1]
irq[2]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

View File

@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
7.703998 network latency _328_/CLK
10.646131 network latency _305_/CLK
---------------
12.353997 16.216131 latency
3.862134 skew
rise -> fall
min max
4.650000 5.570000 source latency
7.734870 network latency _328_/CLK
10.840950 network latency _305_/CLK
---------------
12.384871 16.410950 latency
4.026079 skew
fall -> fall
min max
4.650000 5.570000 source latency
8.003057 network latency _328_/CLK
8.941120 network latency _305_/CLK
---------------
12.653056 14.511120 latency
1.858064 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 10.83 fmax = 92.37

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@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 2.903494e-05 2.930423e-05 5.104404e-07 5.884961e-05 13.7%
Combinational 8.190629e-05 2.169670e-04 3.839341e-06 3.027127e-04 70.5%
Clock 2.463914e-05 4.285167e-05 1.530292e-07 6.764384e-05 15.8%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.355804e-04 2.891229e-04 4.502832e-06 4.292061e-04 100.0%
31.6% 67.4% 1.0%

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===========================================================================
Clock Skew (Setup)
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
Clock clk
10.646008 source latency _296_/CLK ^
-7.888458 target latency _328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.007551 setup skew

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===========================================================================
Clock Skew (Hold)
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
Clock clk
7.895888 source latency _306_/CLK ^
-8.827411 target latency _312_/CLK ^
-0.250000 clock uncertainty
-0.920459 CRPR
--------------
-2.101983 hold skew

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@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
max_ss_100C_1v60: 0.0

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@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
max_ss_100C_1v60: 0.0

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===========================================================================
Violator List
============================================================================

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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
max_ss_100C_1v60: 0.0

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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
max_ss_100C_1v60: 0

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@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
max_ss_100C_1v60: 2.391910737178117

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@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
max_ss_100C_1v60: 1.0005818679036624

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@@ -0,0 +1,763 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= max_tt_025C_1v80 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: _305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 ^ input external delay
2 0.005207 0.000000 0.000000 18.070000 ^ wb_rst_i (in)
wb_rst_i (net)
0.000198 0.000099 18.070099 ^ input37/A (sky130_fd_sc_hd__buf_4)
3 0.111363 0.308423 0.256380 18.326479 ^ input37/X (sky130_fd_sc_hd__buf_4)
net37 (net)
0.321783 0.050331 18.376810 ^ _153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005451 0.072272 0.086494 18.463305 v _153_/Y (sky130_fd_sc_hd__a21oi_4)
_039_ (net)
0.072272 0.000293 18.463598 v hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004987 0.063794 0.575687 19.039284 v hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
net324 (net)
0.063794 0.000343 19.039627 v hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.063174 0.309341 0.806931 19.846560 v hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
net282 (net)
0.309500 0.006496 19.853054 v hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.044986 0.236934 0.850402 20.703457 v hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
net325 (net)
0.236944 0.001791 20.705248 v _160_/A (sky130_fd_sc_hd__nand2_2)
2 0.016700 0.116986 0.178462 20.883709 ^ _160_/Y (sky130_fd_sc_hd__nand2_2)
_044_ (net)
0.117089 0.001881 20.885592 ^ hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.050752 0.497264 0.882233 21.767824 ^ hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
net326 (net)
0.497300 0.004560 21.772383 ^ fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.142286 0.284702 0.322210 22.094593 ^ fanout124/X (sky130_fd_sc_hd__buf_6)
net124 (net)
0.284864 0.006070 22.100664 ^ _161_/A (sky130_fd_sc_hd__inv_2)
2 0.007416 0.061816 0.070321 22.170984 v _161_/Y (sky130_fd_sc_hd__inv_2)
_000_ (net)
0.061819 0.000346 22.171329 v _233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002309 0.038889 0.241434 22.412764 v _233_/X (sky130_fd_sc_hd__a32o_1)
_009_ (net)
0.038889 0.000094 22.412857 v hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002290 0.050240 0.541128 22.953985 v hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
net431 (net)
0.050240 0.000165 22.954151 v hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002847 0.053229 0.550589 23.504740 v hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
net315 (net)
0.053229 0.000211 23.504951 v hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002020 0.049067 0.544267 24.049219 v hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
net432 (net)
0.049067 0.000146 24.049364 v _305_/D (sky130_fd_sc_hd__dfxtp_4)
24.049364 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.032820 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.618827 0.004414 29.654413 ^ wire3/A (sky130_fd_sc_hd__buf_4)
3 0.049956 0.148818 0.305434 29.959846 ^ wire3/X (sky130_fd_sc_hd__buf_4)
net274 (net)
0.149973 0.010555 29.970402 ^ wire2/A (sky130_fd_sc_hd__buf_6)
3 0.112631 0.225562 0.253358 30.223761 ^ wire2/X (sky130_fd_sc_hd__buf_6)
net273 (net)
0.226972 0.014516 30.238277 ^ _155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.055185 0.482949 0.488491 30.726768 ^ _155_/X (sky130_fd_sc_hd__mux2_1)
clk (net)
0.483029 0.005222 30.731991 ^ wire1/A (sky130_fd_sc_hd__buf_4)
3 0.051941 0.152289 0.287500 31.019489 ^ wire1/X (sky130_fd_sc_hd__buf_4)
net272 (net)
0.153434 0.010665 31.030155 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.097480 0.114495 0.218130 31.248285 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_0_clk (net)
0.115440 0.008352 31.256638 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.068926 0.087363 0.183725 31.440363 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_2_2__leaf_clk (net)
0.091346 0.014580 31.454943 ^ _305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 31.204941 clock uncertainty
0.000000 31.204941 clock reconvergence pessimism
-0.103199 31.101742 library setup time
31.101742 data required time
---------------------------------------------------------------------------------------------
31.101742 data required time
-24.049364 data arrival time
---------------------------------------------------------------------------------------------
7.052379 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------------------
_467_/A 1.000000 1.035874 -0.035874 (VIOLATED)
ANTENNA__467__A/DIODE 1.000000 1.035816 -0.035816 (VIOLATED)
_466_/A 1.000000 1.035116 -0.035116 (VIOLATED)
ANTENNA__466__A/DIODE 1.000000 1.035057 -0.035057 (VIOLATED)
_152_/B 1.000000 1.031199 -0.031199 (VIOLATED)
ANTENNA__152__B/DIODE 1.000000 1.031176 -0.031177 (VIOLATED)
_465_/A 1.000000 1.027235 -0.027235 (VIOLATED)
ANTENNA__465__A/DIODE 1.000000 1.027176 -0.027176 (VIOLATED)
ANTENNA_hold48_X/DIODE 1.000000 1.026804 -0.026804 (VIOLATED)
hold48/X 1.000000 1.026782 -0.026782 (VIOLATED)
_464_/A 1.000000 1.011183 -0.011183 (VIOLATED)
ANTENNA__464__A/DIODE 1.000000 1.011124 -0.011124 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
fanout124/X 16 33 -17 (VIOLATED)
fanout125/X 16 33 -17 (VIOLATED)
_159_/Y 16 29 -13 (VIOLATED)
_156_/X 16 27 -11 (VIOLATED)
_195_/X 16 23 -7 (VIOLATED)
_182_/X 16 21 -5 (VIOLATED)
clkbuf_2_2__f_clk/X 16 21 -5 (VIOLATED)
_176_/Y 16 19 -3 (VIOLATED)
_297_/Q 16 19 -3 (VIOLATED)
clkbuf_2_1__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_3__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_0__f_clk/X 16 17 (VIOLATED)
hold140/X 16 17 (VIOLATED)
wire4/X 16 17 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 420 unannotated drivers.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
la_data_in[0]
la_data_in[100]
la_data_in[101]
la_data_in[102]
la_data_in[103]
la_data_in[104]
la_data_in[105]
la_data_in[106]
la_data_in[107]
la_data_in[108]
la_data_in[109]
la_data_in[10]
la_data_in[110]
la_data_in[111]
la_data_in[112]
la_data_in[113]
la_data_in[114]
la_data_in[115]
la_data_in[116]
la_data_in[117]
la_data_in[118]
la_data_in[119]
la_data_in[11]
la_data_in[120]
la_data_in[121]
la_data_in[122]
la_data_in[123]
la_data_in[124]
la_data_in[125]
la_data_in[126]
la_data_in[127]
la_data_in[12]
la_data_in[13]
la_data_in[14]
la_data_in[15]
la_data_in[16]
la_data_in[17]
la_data_in[18]
la_data_in[19]
la_data_in[1]
la_data_in[20]
la_data_in[21]
la_data_in[22]
la_data_in[23]
la_data_in[24]
la_data_in[25]
la_data_in[26]
la_data_in[27]
la_data_in[28]
la_data_in[29]
la_data_in[2]
la_data_in[30]
la_data_in[31]
la_data_in[32]
la_data_in[33]
la_data_in[34]
la_data_in[35]
la_data_in[36]
la_data_in[37]
la_data_in[38]
la_data_in[39]
la_data_in[3]
la_data_in[40]
la_data_in[41]
la_data_in[42]
la_data_in[43]
la_data_in[44]
la_data_in[45]
la_data_in[46]
la_data_in[47]
la_data_in[4]
la_data_in[5]
la_data_in[66]
la_data_in[67]
la_data_in[68]
la_data_in[69]
la_data_in[6]
la_data_in[70]
la_data_in[71]
la_data_in[72]
la_data_in[73]
la_data_in[74]
la_data_in[75]
la_data_in[76]
la_data_in[77]
la_data_in[78]
la_data_in[79]
la_data_in[7]
la_data_in[80]
la_data_in[81]
la_data_in[82]
la_data_in[83]
la_data_in[84]
la_data_in[85]
la_data_in[86]
la_data_in[87]
la_data_in[88]
la_data_in[89]
la_data_in[8]
la_data_in[90]
la_data_in[91]
la_data_in[92]
la_data_in[93]
la_data_in[94]
la_data_in[95]
la_data_in[96]
la_data_in[97]
la_data_in[98]
la_data_in[99]
la_data_in[9]
la_oenb[0]
la_oenb[100]
la_oenb[101]
la_oenb[102]
la_oenb[103]
la_oenb[104]
la_oenb[105]
la_oenb[106]
la_oenb[107]
la_oenb[108]
la_oenb[109]
la_oenb[10]
la_oenb[110]
la_oenb[111]
la_oenb[112]
la_oenb[113]
la_oenb[114]
la_oenb[115]
la_oenb[116]
la_oenb[117]
la_oenb[118]
la_oenb[119]
la_oenb[11]
la_oenb[120]
la_oenb[121]
la_oenb[122]
la_oenb[123]
la_oenb[124]
la_oenb[125]
la_oenb[126]
la_oenb[127]
la_oenb[12]
la_oenb[13]
la_oenb[14]
la_oenb[15]
la_oenb[16]
la_oenb[17]
la_oenb[18]
la_oenb[19]
la_oenb[1]
la_oenb[20]
la_oenb[21]
la_oenb[22]
la_oenb[23]
la_oenb[24]
la_oenb[25]
la_oenb[26]
la_oenb[27]
la_oenb[28]
la_oenb[29]
la_oenb[2]
la_oenb[30]
la_oenb[31]
la_oenb[32]
la_oenb[33]
la_oenb[34]
la_oenb[35]
la_oenb[36]
la_oenb[37]
la_oenb[38]
la_oenb[39]
la_oenb[3]
la_oenb[40]
la_oenb[41]
la_oenb[42]
la_oenb[43]
la_oenb[44]
la_oenb[45]
la_oenb[46]
la_oenb[47]
la_oenb[4]
la_oenb[5]
la_oenb[66]
la_oenb[67]
la_oenb[68]
la_oenb[69]
la_oenb[6]
la_oenb[70]
la_oenb[71]
la_oenb[72]
la_oenb[73]
la_oenb[74]
la_oenb[75]
la_oenb[76]
la_oenb[77]
la_oenb[78]
la_oenb[79]
la_oenb[7]
la_oenb[80]
la_oenb[81]
la_oenb[82]
la_oenb[83]
la_oenb[84]
la_oenb[85]
la_oenb[86]
la_oenb[87]
la_oenb[88]
la_oenb[89]
la_oenb[8]
la_oenb[90]
la_oenb[91]
la_oenb[92]
la_oenb[93]
la_oenb[94]
la_oenb[95]
la_oenb[96]
la_oenb[97]
la_oenb[98]
la_oenb[99]
la_oenb[9]
wbs_adr_i[0]
wbs_adr_i[10]
wbs_adr_i[11]
wbs_adr_i[12]
wbs_adr_i[13]
wbs_adr_i[14]
wbs_adr_i[15]
wbs_adr_i[16]
wbs_adr_i[17]
wbs_adr_i[18]
wbs_adr_i[19]
wbs_adr_i[1]
wbs_adr_i[20]
wbs_adr_i[21]
wbs_adr_i[22]
wbs_adr_i[23]
wbs_adr_i[24]
wbs_adr_i[25]
wbs_adr_i[26]
wbs_adr_i[27]
wbs_adr_i[28]
wbs_adr_i[29]
wbs_adr_i[2]
wbs_adr_i[30]
wbs_adr_i[31]
wbs_adr_i[3]
wbs_adr_i[4]
wbs_adr_i[5]
wbs_adr_i[6]
wbs_adr_i[7]
wbs_adr_i[8]
wbs_adr_i[9]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_sel_i[2]
wbs_sel_i[3]
clkload0/X
clkload1/X
clkload2/X
user_proj_example_141/HI
user_proj_example_142/HI
user_proj_example_143/HI
user_proj_example_144/HI
user_proj_example_145/HI
user_proj_example_146/HI
user_proj_example_147/HI
user_proj_example_148/HI
user_proj_example_149/HI
user_proj_example_150/HI
user_proj_example_151/HI
user_proj_example_152/HI
user_proj_example_153/HI
user_proj_example_154/HI
user_proj_example_155/HI
user_proj_example_156/HI
user_proj_example_157/HI
user_proj_example_158/HI
user_proj_example_159/HI
user_proj_example_160/HI
user_proj_example_161/HI
user_proj_example_162/HI
user_proj_example_163/HI
user_proj_example_164/HI
user_proj_example_165/HI
user_proj_example_166/HI
user_proj_example_167/HI
user_proj_example_168/HI
user_proj_example_169/HI
user_proj_example_170/HI
user_proj_example_171/HI
user_proj_example_172/HI
user_proj_example_173/HI
user_proj_example_174/HI
user_proj_example_175/HI
user_proj_example_176/HI
user_proj_example_177/HI
user_proj_example_178/HI
user_proj_example_179/HI
user_proj_example_180/HI
user_proj_example_181/HI
user_proj_example_182/HI
user_proj_example_183/HI
user_proj_example_184/HI
user_proj_example_185/HI
user_proj_example_186/HI
user_proj_example_187/HI
user_proj_example_188/HI
user_proj_example_189/HI
user_proj_example_190/HI
user_proj_example_191/HI
user_proj_example_192/HI
user_proj_example_193/HI
user_proj_example_194/HI
user_proj_example_195/HI
user_proj_example_196/HI
user_proj_example_197/HI
user_proj_example_198/HI
user_proj_example_199/HI
user_proj_example_200/HI
user_proj_example_201/HI
user_proj_example_202/HI
user_proj_example_203/HI
user_proj_example_204/HI
user_proj_example_205/HI
user_proj_example_206/HI
user_proj_example_207/HI
user_proj_example_208/HI
user_proj_example_209/HI
user_proj_example_210/HI
user_proj_example_211/HI
user_proj_example_212/HI
user_proj_example_213/HI
user_proj_example_214/HI
user_proj_example_215/HI
user_proj_example_216/HI
user_proj_example_217/HI
user_proj_example_218/HI
user_proj_example_219/HI
user_proj_example_220/HI
user_proj_example_221/HI
user_proj_example_222/HI
user_proj_example_223/HI
user_proj_example_224/HI
user_proj_example_225/HI
user_proj_example_226/HI
user_proj_example_227/HI
user_proj_example_228/HI
user_proj_example_229/HI
user_proj_example_230/HI
user_proj_example_231/HI
user_proj_example_232/HI
user_proj_example_233/HI
user_proj_example_234/HI
user_proj_example_235/HI
user_proj_example_236/HI
user_proj_example_237/HI
user_proj_example_238/HI
user_proj_example_239/HI
user_proj_example_240/HI
user_proj_example_241/HI
user_proj_example_242/HI
user_proj_example_243/HI
user_proj_example_244/HI
user_proj_example_245/HI
user_proj_example_246/HI
user_proj_example_247/HI
user_proj_example_248/HI
user_proj_example_249/HI
user_proj_example_250/HI
user_proj_example_251/HI
user_proj_example_252/HI
user_proj_example_253/HI
user_proj_example_254/HI
user_proj_example_255/HI
user_proj_example_256/HI
user_proj_example_257/HI
user_proj_example_258/HI
user_proj_example_259/HI
user_proj_example_260/HI
user_proj_example_261/HI
user_proj_example_262/HI
user_proj_example_263/HI
user_proj_example_264/HI
user_proj_example_265/HI
user_proj_example_266/HI
user_proj_example_267/HI
user_proj_example_268/HI
user_proj_example_269/HI
user_proj_example_270/HI
user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 12
max fanout violation count 14
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 16 input ports missing set_input_delay.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
Warning: There are 163 unconstrained endpoints.
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[1]
io_oeb[2]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[1]
io_out[2]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
irq[0]
irq[1]
irq[2]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

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@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
6.422780 network latency _328_/CLK
9.348904 network latency _305_/CLK
---------------
11.072780 14.918904 latency
3.846124 skew
rise -> fall
min max
4.650000 5.570000 source latency
6.393727 network latency _328_/CLK
9.341233 network latency _305_/CLK
---------------
11.043728 14.911234 latency
3.867506 skew
fall -> fall
min max
4.650000 5.570000 source latency
6.519397 network latency _328_/CLK
7.453887 network latency _305_/CLK
---------------
11.169396 13.023887 latency
1.854490 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 5.49 fmax = 182.10

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===========================================================================
report_power
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 3.688020e-05 3.715193e-05 2.838373e-10 7.403241e-05 13.8%
Combinational 1.019080e-04 2.747049e-04 3.073229e-09 3.766160e-04 70.4%
Clock 3.016750e-05 5.416015e-05 4.242312e-09 8.433190e-05 15.8%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.689556e-04 3.660170e-04 7.599371e-09 5.349802e-04 100.0%
31.6% 68.4% 0.0%

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===========================================================================
Clock Skew (Setup)
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
Clock clk
9.348785 source latency _296_/CLK ^
-6.438337 target latency _328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.160449 setup skew

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===========================================================================
Clock Skew (Hold)
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
Clock clk
6.442685 source latency _306_/CLK ^
-7.373771 target latency _312_/CLK ^
-0.250000 clock uncertainty
-0.920140 CRPR
--------------
-2.101227 hold skew

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===========================================================================
Total Negative Slack (Setup)
============================================================================
max_tt_025C_1v80: 0.0

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===========================================================================
Total Negative Slack (Hold)
============================================================================
max_tt_025C_1v80: 0.0

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===========================================================================
Violator List
============================================================================

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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
max_tt_025C_1v80: 0.0

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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
max_tt_025C_1v80: 0

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@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
max_tt_025C_1v80: 7.0523784364040365

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
max_tt_025C_1v80: 0.3314753010342061

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@@ -0,0 +1,746 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= min_ff_n40C_1v95 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: _305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 v input external delay
2 0.004593 0.000000 0.000000 18.070000 v wb_rst_i (in)
wb_rst_i (net)
0.000050 0.000025 18.070024 v input37/A (sky130_fd_sc_hd__buf_4)
3 0.098721 0.091811 0.130134 18.200159 v input37/X (sky130_fd_sc_hd__buf_4)
net37 (net)
0.105467 0.026697 18.226854 v _153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005116 0.072899 0.104114 18.330969 ^ _153_/Y (sky130_fd_sc_hd__a21oi_4)
_039_ (net)
0.072900 0.000099 18.331068 ^ hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004676 0.049993 0.389726 18.720795 ^ hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
net324 (net)
0.049993 0.000083 18.720879 ^ hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.058232 0.435321 0.658515 19.379393 ^ hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
net282 (net)
0.435322 0.001776 19.381168 ^ hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.040854 0.308938 0.593872 19.975040 ^ hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
net325 (net)
0.308938 0.000522 19.975563 ^ _160_/A (sky130_fd_sc_hd__nand2_2)
2 0.014720 0.091891 0.067043 20.042606 v _160_/Y (sky130_fd_sc_hd__nand2_2)
_044_ (net)
0.091902 0.000759 20.043365 v hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.044886 0.163908 0.514147 20.557512 v hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
net326 (net)
0.163917 0.001330 20.558842 v fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.128472 0.084558 0.175357 20.734200 v fanout124/X (sky130_fd_sc_hd__buf_6)
net124 (net)
0.084568 0.000806 20.735006 v _161_/A (sky130_fd_sc_hd__inv_2)
2 0.007256 0.038757 0.057851 20.792856 ^ _161_/Y (sky130_fd_sc_hd__inv_2)
_000_ (net)
0.038757 0.000048 20.792904 ^ _233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002475 0.035375 0.082816 20.875719 ^ _233_/X (sky130_fd_sc_hd__a32o_1)
_009_ (net)
0.035375 0.000014 20.875734 ^ hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002425 0.035111 0.369329 21.245064 ^ hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
net431 (net)
0.035111 0.000025 21.245089 ^ hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002915 0.038074 0.372408 21.617496 ^ hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
net315 (net)
0.038074 0.000034 21.617529 ^ hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002098 0.033302 0.367811 21.985340 ^ hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
net432 (net)
0.033302 0.000020 21.985359 ^ _305_/D (sky130_fd_sc_hd__dfxtp_4)
21.985359 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.029254 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.615155 0.002577 29.652576 ^ wire3/A (sky130_fd_sc_hd__buf_4)
3 0.043568 0.101185 0.151804 29.804380 ^ wire3/X (sky130_fd_sc_hd__buf_4)
net274 (net)
0.101622 0.005279 29.809660 ^ wire2/A (sky130_fd_sc_hd__buf_6)
3 0.098274 0.148670 0.159492 29.969152 ^ wire2/X (sky130_fd_sc_hd__buf_6)
net273 (net)
0.149031 0.005997 29.975149 ^ _155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.049782 0.327862 0.307587 30.282736 ^ _155_/X (sky130_fd_sc_hd__mux2_1)
clk (net)
0.327878 0.001886 30.284622 ^ wire1/A (sky130_fd_sc_hd__buf_4)
3 0.046498 0.103382 0.155872 30.440495 ^ wire1/X (sky130_fd_sc_hd__buf_4)
net272 (net)
0.103828 0.005450 30.445944 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.090564 0.082419 0.143014 30.588959 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_0_clk (net)
0.082737 0.004089 30.593048 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.062058 0.061268 0.122292 30.715338 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_2_2__leaf_clk (net)
0.061823 0.004572 30.719912 ^ _305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 30.469910 clock uncertainty
0.000000 30.469910 clock reconvergence pessimism
-0.030882 30.439030 library setup time
30.439030 data required time
---------------------------------------------------------------------------------------------
30.439030 data required time
-21.985359 data arrival time
---------------------------------------------------------------------------------------------
8.453670 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
fanout124/X 16 33 -17 (VIOLATED)
fanout125/X 16 33 -17 (VIOLATED)
_159_/Y 16 29 -13 (VIOLATED)
_156_/X 16 27 -11 (VIOLATED)
_195_/X 16 23 -7 (VIOLATED)
_182_/X 16 21 -5 (VIOLATED)
clkbuf_2_2__f_clk/X 16 21 -5 (VIOLATED)
_176_/Y 16 19 -3 (VIOLATED)
_297_/Q 16 19 -3 (VIOLATED)
clkbuf_2_1__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_3__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_0__f_clk/X 16 17 (VIOLATED)
hold140/X 16 17 (VIOLATED)
wire4/X 16 17 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 420 unannotated drivers.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
la_data_in[0]
la_data_in[100]
la_data_in[101]
la_data_in[102]
la_data_in[103]
la_data_in[104]
la_data_in[105]
la_data_in[106]
la_data_in[107]
la_data_in[108]
la_data_in[109]
la_data_in[10]
la_data_in[110]
la_data_in[111]
la_data_in[112]
la_data_in[113]
la_data_in[114]
la_data_in[115]
la_data_in[116]
la_data_in[117]
la_data_in[118]
la_data_in[119]
la_data_in[11]
la_data_in[120]
la_data_in[121]
la_data_in[122]
la_data_in[123]
la_data_in[124]
la_data_in[125]
la_data_in[126]
la_data_in[127]
la_data_in[12]
la_data_in[13]
la_data_in[14]
la_data_in[15]
la_data_in[16]
la_data_in[17]
la_data_in[18]
la_data_in[19]
la_data_in[1]
la_data_in[20]
la_data_in[21]
la_data_in[22]
la_data_in[23]
la_data_in[24]
la_data_in[25]
la_data_in[26]
la_data_in[27]
la_data_in[28]
la_data_in[29]
la_data_in[2]
la_data_in[30]
la_data_in[31]
la_data_in[32]
la_data_in[33]
la_data_in[34]
la_data_in[35]
la_data_in[36]
la_data_in[37]
la_data_in[38]
la_data_in[39]
la_data_in[3]
la_data_in[40]
la_data_in[41]
la_data_in[42]
la_data_in[43]
la_data_in[44]
la_data_in[45]
la_data_in[46]
la_data_in[47]
la_data_in[4]
la_data_in[5]
la_data_in[66]
la_data_in[67]
la_data_in[68]
la_data_in[69]
la_data_in[6]
la_data_in[70]
la_data_in[71]
la_data_in[72]
la_data_in[73]
la_data_in[74]
la_data_in[75]
la_data_in[76]
la_data_in[77]
la_data_in[78]
la_data_in[79]
la_data_in[7]
la_data_in[80]
la_data_in[81]
la_data_in[82]
la_data_in[83]
la_data_in[84]
la_data_in[85]
la_data_in[86]
la_data_in[87]
la_data_in[88]
la_data_in[89]
la_data_in[8]
la_data_in[90]
la_data_in[91]
la_data_in[92]
la_data_in[93]
la_data_in[94]
la_data_in[95]
la_data_in[96]
la_data_in[97]
la_data_in[98]
la_data_in[99]
la_data_in[9]
la_oenb[0]
la_oenb[100]
la_oenb[101]
la_oenb[102]
la_oenb[103]
la_oenb[104]
la_oenb[105]
la_oenb[106]
la_oenb[107]
la_oenb[108]
la_oenb[109]
la_oenb[10]
la_oenb[110]
la_oenb[111]
la_oenb[112]
la_oenb[113]
la_oenb[114]
la_oenb[115]
la_oenb[116]
la_oenb[117]
la_oenb[118]
la_oenb[119]
la_oenb[11]
la_oenb[120]
la_oenb[121]
la_oenb[122]
la_oenb[123]
la_oenb[124]
la_oenb[125]
la_oenb[126]
la_oenb[127]
la_oenb[12]
la_oenb[13]
la_oenb[14]
la_oenb[15]
la_oenb[16]
la_oenb[17]
la_oenb[18]
la_oenb[19]
la_oenb[1]
la_oenb[20]
la_oenb[21]
la_oenb[22]
la_oenb[23]
la_oenb[24]
la_oenb[25]
la_oenb[26]
la_oenb[27]
la_oenb[28]
la_oenb[29]
la_oenb[2]
la_oenb[30]
la_oenb[31]
la_oenb[32]
la_oenb[33]
la_oenb[34]
la_oenb[35]
la_oenb[36]
la_oenb[37]
la_oenb[38]
la_oenb[39]
la_oenb[3]
la_oenb[40]
la_oenb[41]
la_oenb[42]
la_oenb[43]
la_oenb[44]
la_oenb[45]
la_oenb[46]
la_oenb[47]
la_oenb[4]
la_oenb[5]
la_oenb[66]
la_oenb[67]
la_oenb[68]
la_oenb[69]
la_oenb[6]
la_oenb[70]
la_oenb[71]
la_oenb[72]
la_oenb[73]
la_oenb[74]
la_oenb[75]
la_oenb[76]
la_oenb[77]
la_oenb[78]
la_oenb[79]
la_oenb[7]
la_oenb[80]
la_oenb[81]
la_oenb[82]
la_oenb[83]
la_oenb[84]
la_oenb[85]
la_oenb[86]
la_oenb[87]
la_oenb[88]
la_oenb[89]
la_oenb[8]
la_oenb[90]
la_oenb[91]
la_oenb[92]
la_oenb[93]
la_oenb[94]
la_oenb[95]
la_oenb[96]
la_oenb[97]
la_oenb[98]
la_oenb[99]
la_oenb[9]
wbs_adr_i[0]
wbs_adr_i[10]
wbs_adr_i[11]
wbs_adr_i[12]
wbs_adr_i[13]
wbs_adr_i[14]
wbs_adr_i[15]
wbs_adr_i[16]
wbs_adr_i[17]
wbs_adr_i[18]
wbs_adr_i[19]
wbs_adr_i[1]
wbs_adr_i[20]
wbs_adr_i[21]
wbs_adr_i[22]
wbs_adr_i[23]
wbs_adr_i[24]
wbs_adr_i[25]
wbs_adr_i[26]
wbs_adr_i[27]
wbs_adr_i[28]
wbs_adr_i[29]
wbs_adr_i[2]
wbs_adr_i[30]
wbs_adr_i[31]
wbs_adr_i[3]
wbs_adr_i[4]
wbs_adr_i[5]
wbs_adr_i[6]
wbs_adr_i[7]
wbs_adr_i[8]
wbs_adr_i[9]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_sel_i[2]
wbs_sel_i[3]
clkload0/X
clkload1/X
clkload2/X
user_proj_example_141/HI
user_proj_example_142/HI
user_proj_example_143/HI
user_proj_example_144/HI
user_proj_example_145/HI
user_proj_example_146/HI
user_proj_example_147/HI
user_proj_example_148/HI
user_proj_example_149/HI
user_proj_example_150/HI
user_proj_example_151/HI
user_proj_example_152/HI
user_proj_example_153/HI
user_proj_example_154/HI
user_proj_example_155/HI
user_proj_example_156/HI
user_proj_example_157/HI
user_proj_example_158/HI
user_proj_example_159/HI
user_proj_example_160/HI
user_proj_example_161/HI
user_proj_example_162/HI
user_proj_example_163/HI
user_proj_example_164/HI
user_proj_example_165/HI
user_proj_example_166/HI
user_proj_example_167/HI
user_proj_example_168/HI
user_proj_example_169/HI
user_proj_example_170/HI
user_proj_example_171/HI
user_proj_example_172/HI
user_proj_example_173/HI
user_proj_example_174/HI
user_proj_example_175/HI
user_proj_example_176/HI
user_proj_example_177/HI
user_proj_example_178/HI
user_proj_example_179/HI
user_proj_example_180/HI
user_proj_example_181/HI
user_proj_example_182/HI
user_proj_example_183/HI
user_proj_example_184/HI
user_proj_example_185/HI
user_proj_example_186/HI
user_proj_example_187/HI
user_proj_example_188/HI
user_proj_example_189/HI
user_proj_example_190/HI
user_proj_example_191/HI
user_proj_example_192/HI
user_proj_example_193/HI
user_proj_example_194/HI
user_proj_example_195/HI
user_proj_example_196/HI
user_proj_example_197/HI
user_proj_example_198/HI
user_proj_example_199/HI
user_proj_example_200/HI
user_proj_example_201/HI
user_proj_example_202/HI
user_proj_example_203/HI
user_proj_example_204/HI
user_proj_example_205/HI
user_proj_example_206/HI
user_proj_example_207/HI
user_proj_example_208/HI
user_proj_example_209/HI
user_proj_example_210/HI
user_proj_example_211/HI
user_proj_example_212/HI
user_proj_example_213/HI
user_proj_example_214/HI
user_proj_example_215/HI
user_proj_example_216/HI
user_proj_example_217/HI
user_proj_example_218/HI
user_proj_example_219/HI
user_proj_example_220/HI
user_proj_example_221/HI
user_proj_example_222/HI
user_proj_example_223/HI
user_proj_example_224/HI
user_proj_example_225/HI
user_proj_example_226/HI
user_proj_example_227/HI
user_proj_example_228/HI
user_proj_example_229/HI
user_proj_example_230/HI
user_proj_example_231/HI
user_proj_example_232/HI
user_proj_example_233/HI
user_proj_example_234/HI
user_proj_example_235/HI
user_proj_example_236/HI
user_proj_example_237/HI
user_proj_example_238/HI
user_proj_example_239/HI
user_proj_example_240/HI
user_proj_example_241/HI
user_proj_example_242/HI
user_proj_example_243/HI
user_proj_example_244/HI
user_proj_example_245/HI
user_proj_example_246/HI
user_proj_example_247/HI
user_proj_example_248/HI
user_proj_example_249/HI
user_proj_example_250/HI
user_proj_example_251/HI
user_proj_example_252/HI
user_proj_example_253/HI
user_proj_example_254/HI
user_proj_example_255/HI
user_proj_example_256/HI
user_proj_example_257/HI
user_proj_example_258/HI
user_proj_example_259/HI
user_proj_example_260/HI
user_proj_example_261/HI
user_proj_example_262/HI
user_proj_example_263/HI
user_proj_example_264/HI
user_proj_example_265/HI
user_proj_example_266/HI
user_proj_example_267/HI
user_proj_example_268/HI
user_proj_example_269/HI
user_proj_example_270/HI
user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 14
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 16 input ports missing set_input_delay.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
Warning: There are 163 unconstrained endpoints.
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[1]
io_oeb[2]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[1]
io_out[2]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
irq[0]
irq[1]
irq[2]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

View File

@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
5.712397 network latency _328_/CLK
8.719483 network latency _305_/CLK
---------------
10.362397 14.289484 latency
3.927086 skew
rise -> fall
min max
4.650000 5.570000 source latency
5.803298 network latency _328_/CLK
8.714544 network latency _305_/CLK
---------------
10.453298 14.284544 latency
3.831246 skew
fall -> fall
min max
4.650000 5.570000 source latency
5.860418 network latency _328_/CLK
6.789245 network latency _305_/CLK
---------------
10.510418 12.359244 latency
1.848827 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 3.59 fmax = 278.22

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@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 4.252898e-05 3.918598e-05 7.394261e-10 8.171570e-05 13.6%
Combinational 1.179006e-04 3.079596e-04 1.315145e-08 4.258733e-04 71.1%
Clock 3.452234e-05 5.678719e-05 5.304953e-09 9.131483e-05 15.2%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.949518e-04 4.039328e-04 1.919599e-08 5.989038e-04 100.0%
32.6% 67.4% 0.0%

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@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
Clock clk
8.719459 source latency _296_/CLK ^
-5.712397 target latency _328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.257061 setup skew

View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
Clock clk
5.714611 source latency _306_/CLK ^
-6.639090 target latency _312_/CLK ^
-0.250000 clock uncertainty
-0.920002 CRPR
--------------
-2.094481 hold skew

View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
min_ff_n40C_1v95: 0.0

View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
min_ff_n40C_1v95: 0.0

View File

@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
min_ff_n40C_1v95: 0.0

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
min_ff_n40C_1v95: 0

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
min_ff_n40C_1v95: 8.453670003294032

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
min_ff_n40C_1v95: 0.3001150524152958

View File

@@ -0,0 +1,871 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= min_ss_100C_1v60 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: _305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 ^ input external delay
2 0.005038 0.000000 0.000000 18.070000 ^ wb_rst_i (in)
wb_rst_i (net)
0.000055 0.000028 18.070028 ^ input37/A (sky130_fd_sc_hd__buf_4)
3 0.099860 0.439302 0.430967 18.500996 ^ input37/X (sky130_fd_sc_hd__buf_4)
net37 (net)
0.442170 0.028844 18.529840 ^ _153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.004786 0.108086 0.206688 18.736528 v _153_/Y (sky130_fd_sc_hd__a21oi_4)
_039_ (net)
0.108086 0.000092 18.736620 v hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004346 0.123835 1.167580 19.904200 v hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
net324 (net)
0.123835 0.000076 19.904276 v hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.057596 0.555790 1.599441 21.503717 v hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
net282 (net)
0.555790 0.001743 21.505459 v hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.040745 0.416333 1.701606 23.207066 v hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
net325 (net)
0.416333 0.000517 23.207582 v _160_/A (sky130_fd_sc_hd__nand2_2)
2 0.014913 0.182853 0.298957 23.506540 ^ _160_/Y (sky130_fd_sc_hd__nand2_2)
_044_ (net)
0.182853 0.000773 23.507313 ^ hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.045904 0.695979 1.558522 25.065834 ^ hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
net326 (net)
0.695979 0.001384 25.067219 ^ fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.131531 0.413820 0.641734 25.708952 ^ fanout124/X (sky130_fd_sc_hd__buf_6)
net124 (net)
0.413822 0.000828 25.709780 ^ _161_/A (sky130_fd_sc_hd__inv_2)
2 0.006802 0.092105 0.169885 25.879665 v _161_/Y (sky130_fd_sc_hd__inv_2)
_000_ (net)
0.092105 0.000046 25.879711 v _233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002145 0.067688 0.433655 26.313366 v _233_/X (sky130_fd_sc_hd__a32o_1)
_009_ (net)
0.067688 0.000012 26.313379 v hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002095 0.101935 1.110495 27.423874 v hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
net431 (net)
0.101935 0.000021 27.423895 v hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002585 0.103909 1.134758 28.558653 v hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
net315 (net)
0.103909 0.000030 28.558683 v hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.001834 0.098867 1.122999 29.681683 v hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
net432 (net)
0.098867 0.000016 29.681698 v _305_/D (sky130_fd_sc_hd__dfxtp_4)
29.681698 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.029405 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.615199 0.002601 29.652599 ^ wire3/A (sky130_fd_sc_hd__buf_4)
3 0.043881 0.208057 0.536472 30.189072 ^ wire3/X (sky130_fd_sc_hd__buf_4)
net274 (net)
0.208218 0.005318 30.194389 ^ wire2/A (sky130_fd_sc_hd__buf_6)
3 0.098501 0.312768 0.421259 30.615650 ^ wire2/X (sky130_fd_sc_hd__buf_6)
net273 (net)
0.313039 0.006011 30.621660 ^ _155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.050135 0.697929 0.799332 31.420994 ^ _155_/X (sky130_fd_sc_hd__mux2_1)
clk (net)
0.697929 0.001894 31.422886 ^ wire1/A (sky130_fd_sc_hd__buf_4)
3 0.046833 0.221061 0.568903 31.991789 ^ wire1/X (sky130_fd_sc_hd__buf_4)
net272 (net)
0.221218 0.005492 31.997282 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.091298 0.163726 0.373870 32.371151 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_0_clk (net)
0.163845 0.004135 32.375286 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.062250 0.123517 0.316668 32.691956 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_2_2__leaf_clk (net)
0.123902 0.004572 32.696526 ^ _305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 32.446526 clock uncertainty
0.000000 32.446526 clock reconvergence pessimism
-0.270404 32.176121 library setup time
32.176121 data required time
---------------------------------------------------------------------------------------------
32.176121 data required time
-29.681698 data arrival time
---------------------------------------------------------------------------------------------
2.494424 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------------------
_152_/B 1.000000 1.378951 -0.378951 (VIOLATED)
ANTENNA__152__B/DIODE 1.000000 1.378949 -0.378949 (VIOLATED)
ANTENNA_hold48_X/DIODE 1.000000 1.377366 -0.377366 (VIOLATED)
hold48/X 1.000000 1.377366 -0.377366 (VIOLATED)
ANTENNA__206__B1/DIODE 1.000000 1.281471 -0.281471 (VIOLATED)
ANTENNA_hold133_X/DIODE 1.000000 1.281471 -0.281471 (VIOLATED)
_206_/B1 1.000000 1.281471 -0.281471 (VIOLATED)
hold133/X 1.000000 1.281471 -0.281471 (VIOLATED)
ANTENNA__246__A2/DIODE 1.000000 1.240362 -0.240362 (VIOLATED)
_246_/A2 1.000000 1.240362 -0.240362 (VIOLATED)
ANTENNA_hold11_X/DIODE 1.000000 1.240172 -0.240172 (VIOLATED)
hold11/X 1.000000 1.240172 -0.240172 (VIOLATED)
_163_/A2 1.000000 1.155503 -0.155503 (VIOLATED)
ANTENNA__163__A2/DIODE 1.000000 1.155503 -0.155503 (VIOLATED)
_164_/A2 1.000000 1.155503 -0.155503 (VIOLATED)
ANTENNA__164__A2/DIODE 1.000000 1.155500 -0.155500 (VIOLATED)
_224_/A_N 1.000000 1.155491 -0.155491 (VIOLATED)
ANTENNA__224__A_N/DIODE 1.000000 1.155489 -0.155489 (VIOLATED)
ANTENNA_hold138_X/DIODE 1.000000 1.155339 -0.155339 (VIOLATED)
hold138/X 1.000000 1.155339 -0.155339 (VIOLATED)
_264_/B 1.000000 1.133621 -0.133621 (VIOLATED)
ANTENNA__264__B/DIODE 1.000000 1.133618 -0.133618 (VIOLATED)
_269_/B 1.000000 1.133614 -0.133614 (VIOLATED)
ANTENNA__269__B/DIODE 1.000000 1.133605 -0.133605 (VIOLATED)
_252_/B 1.000000 1.133539 -0.133539 (VIOLATED)
ANTENNA__252__B/DIODE 1.000000 1.133513 -0.133513 (VIOLATED)
ANTENNA__237__B/DIODE 1.000000 1.133303 -0.133303 (VIOLATED)
_237_/B 1.000000 1.133246 -0.133246 (VIOLATED)
_215_/B 1.000000 1.132818 -0.132818 (VIOLATED)
ANTENNA__215__B/DIODE 1.000000 1.132794 -0.132794 (VIOLATED)
_169_/B1 1.000000 1.132505 -0.132505 (VIOLATED)
ANTENNA__169__B1/DIODE 1.000000 1.132456 -0.132456 (VIOLATED)
ANTENNA__168__B1/DIODE 1.000000 1.132400 -0.132400 (VIOLATED)
_168_/B1 1.000000 1.132362 -0.132362 (VIOLATED)
_198_/B 1.000000 1.132038 -0.132038 (VIOLATED)
ANTENNA__198__B/DIODE 1.000000 1.131955 -0.131955 (VIOLATED)
_190_/B 1.000000 1.131652 -0.131652 (VIOLATED)
ANTENNA__190__B/DIODE 1.000000 1.131644 -0.131644 (VIOLATED)
ANTENNA__253__B1/DIODE 1.000000 1.126029 -0.126030 (VIOLATED)
ANTENNA_hold81_X/DIODE 1.000000 1.126029 -0.126030 (VIOLATED)
_253_/B1 1.000000 1.126029 -0.126030 (VIOLATED)
hold81/X 1.000000 1.126029 -0.126030 (VIOLATED)
_173_/B 1.000000 1.115463 -0.115464 (VIOLATED)
ANTENNA__173__B/DIODE 1.000000 1.115400 -0.115400 (VIOLATED)
_164_/B1 1.000000 1.115053 -0.115053 (VIOLATED)
ANTENNA__164__B1/DIODE 1.000000 1.114835 -0.114835 (VIOLATED)
_163_/B1 1.000000 1.114657 -0.114657 (VIOLATED)
ANTENNA__163__B1/DIODE 1.000000 1.114657 -0.114657 (VIOLATED)
_170_/B 1.000000 1.114655 -0.114655 (VIOLATED)
ANTENNA__170__B/DIODE 1.000000 1.114548 -0.114548 (VIOLATED)
ANTENNA__156__X/DIODE 1.000000 1.109280 -0.109280 (VIOLATED)
_156_/X 1.000000 1.109275 -0.109275 (VIOLATED)
ANTENNA__265__B1/DIODE 1.000000 1.063149 -0.063149 (VIOLATED)
ANTENNA_hold66_X/DIODE 1.000000 1.063149 -0.063149 (VIOLATED)
_265_/B1 1.000000 1.063149 -0.063149 (VIOLATED)
hold66/X 1.000000 1.063149 -0.063149 (VIOLATED)
wire134/A 1.000000 1.033586 -0.033586 (VIOLATED)
ANTENNA__187__A1/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA__191__A1/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA__199__A1/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA__216__A1/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA__226__A1/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA__253__A1/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA__265__A1/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA__270__A1/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA_hold140_X/DIODE 1.000000 1.033582 -0.033582 (VIOLATED)
_187_/A1 1.000000 1.033582 -0.033582 (VIOLATED)
_191_/A1 1.000000 1.033582 -0.033582 (VIOLATED)
_199_/A1 1.000000 1.033582 -0.033582 (VIOLATED)
_216_/A1 1.000000 1.033582 -0.033582 (VIOLATED)
_226_/A1 1.000000 1.033582 -0.033582 (VIOLATED)
_253_/A1 1.000000 1.033582 -0.033582 (VIOLATED)
_265_/A1 1.000000 1.033582 -0.033582 (VIOLATED)
_270_/A1 1.000000 1.033582 -0.033582 (VIOLATED)
hold140/X 1.000000 1.033582 -0.033582 (VIOLATED)
ANTENNA_wire134_A/DIODE 1.000000 1.033577 -0.033577 (VIOLATED)
ANTENNA__191__B1/DIODE 1.000000 1.033317 -0.033317 (VIOLATED)
_191_/B1 1.000000 1.033316 -0.033316 (VIOLATED)
ANTENNA_hold61_X/DIODE 1.000000 1.033003 -0.033003 (VIOLATED)
hold61/X 1.000000 1.033003 -0.033003 (VIOLATED)
output77/A 1.000000 1.030317 -0.030317 (VIOLATED)
ANTENNA_output77_A/DIODE 1.000000 1.030307 -0.030307 (VIOLATED)
_285_/A0 1.000000 1.029844 -0.029844 (VIOLATED)
ANTENNA__285__A0/DIODE 1.000000 1.029844 -0.029844 (VIOLATED)
_221_/B 1.000000 1.028978 -0.028978 (VIOLATED)
ANTENNA__221__B/DIODE 1.000000 1.028971 -0.028971 (VIOLATED)
hold129/A 1.000000 1.028939 -0.028939 (VIOLATED)
ANTENNA_hold129_A/DIODE 1.000000 1.028937 -0.028937 (VIOLATED)
ANTENNA__209__B1/DIODE 1.000000 1.028914 -0.028914 (VIOLATED)
_209_/B1 1.000000 1.028912 -0.028912 (VIOLATED)
_208_/B 1.000000 1.028907 -0.028907 (VIOLATED)
ANTENNA__208__B/DIODE 1.000000 1.028905 -0.028905 (VIOLATED)
ANTENNA__302__Q/DIODE 1.000000 1.028903 -0.028903 (VIOLATED)
_302_/Q 1.000000 1.028900 -0.028900 (VIOLATED)
wire136/A 1.000000 1.021125 -0.021125 (VIOLATED)
ANTENNA_wire136_A/DIODE 1.000000 1.021121 -0.021121 (VIOLATED)
_291_/A0 1.000000 1.019881 -0.019882 (VIOLATED)
ANTENNA__291__A0/DIODE 1.000000 1.019880 -0.019880 (VIOLATED)
ANTENNA__248__D/DIODE 1.000000 1.019662 -0.019662 (VIOLATED)
ANTENNA__250__B1/DIODE 1.000000 1.019662 -0.019662 (VIOLATED)
ANTENNA__308__Q/DIODE 1.000000 1.019662 -0.019662 (VIOLATED)
ANTENNA_hold125_A/DIODE 1.000000 1.019662 -0.019662 (VIOLATED)
_248_/D 1.000000 1.019662 -0.019662 (VIOLATED)
_250_/B1 1.000000 1.019662 -0.019662 (VIOLATED)
_308_/Q 1.000000 1.019662 -0.019662 (VIOLATED)
hold125/A 1.000000 1.019662 -0.019662 (VIOLATED)
_283_/A0 1.000000 1.019615 -0.019615 (VIOLATED)
ANTENNA__283__A0/DIODE 1.000000 1.019615 -0.019615 (VIOLATED)
ANTENNA__195__D/DIODE 1.000000 1.019513 -0.019513 (VIOLATED)
_195_/D 1.000000 1.019513 -0.019513 (VIOLATED)
hold127/A 1.000000 1.019501 -0.019501 (VIOLATED)
ANTENNA_hold127_A/DIODE 1.000000 1.019497 -0.019497 (VIOLATED)
ANTENNA__300__Q/DIODE 1.000000 1.019491 -0.019491 (VIOLATED)
ANTENNA__196__B1/DIODE 1.000000 1.019489 -0.019489 (VIOLATED)
_196_/B1 1.000000 1.019489 -0.019489 (VIOLATED)
_300_/Q 1.000000 1.019489 -0.019489 (VIOLATED)
ANTENNA__238__A2/DIODE 1.000000 1.004065 -0.004065 (VIOLATED)
ANTENNA_hold76_X/DIODE 1.000000 1.004065 -0.004065 (VIOLATED)
_238_/A2 1.000000 1.004065 -0.004065 (VIOLATED)
hold76/X 1.000000 1.004065 -0.004065 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
fanout124/X 16 33 -17 (VIOLATED)
fanout125/X 16 33 -17 (VIOLATED)
_159_/Y 16 29 -13 (VIOLATED)
_156_/X 16 27 -11 (VIOLATED)
_195_/X 16 23 -7 (VIOLATED)
_182_/X 16 21 -5 (VIOLATED)
clkbuf_2_2__f_clk/X 16 21 -5 (VIOLATED)
_176_/Y 16 19 -3 (VIOLATED)
_297_/Q 16 19 -3 (VIOLATED)
clkbuf_2_1__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_3__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_0__f_clk/X 16 17 (VIOLATED)
hold140/X 16 17 (VIOLATED)
wire4/X 16 17 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 420 unannotated drivers.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
la_data_in[0]
la_data_in[100]
la_data_in[101]
la_data_in[102]
la_data_in[103]
la_data_in[104]
la_data_in[105]
la_data_in[106]
la_data_in[107]
la_data_in[108]
la_data_in[109]
la_data_in[10]
la_data_in[110]
la_data_in[111]
la_data_in[112]
la_data_in[113]
la_data_in[114]
la_data_in[115]
la_data_in[116]
la_data_in[117]
la_data_in[118]
la_data_in[119]
la_data_in[11]
la_data_in[120]
la_data_in[121]
la_data_in[122]
la_data_in[123]
la_data_in[124]
la_data_in[125]
la_data_in[126]
la_data_in[127]
la_data_in[12]
la_data_in[13]
la_data_in[14]
la_data_in[15]
la_data_in[16]
la_data_in[17]
la_data_in[18]
la_data_in[19]
la_data_in[1]
la_data_in[20]
la_data_in[21]
la_data_in[22]
la_data_in[23]
la_data_in[24]
la_data_in[25]
la_data_in[26]
la_data_in[27]
la_data_in[28]
la_data_in[29]
la_data_in[2]
la_data_in[30]
la_data_in[31]
la_data_in[32]
la_data_in[33]
la_data_in[34]
la_data_in[35]
la_data_in[36]
la_data_in[37]
la_data_in[38]
la_data_in[39]
la_data_in[3]
la_data_in[40]
la_data_in[41]
la_data_in[42]
la_data_in[43]
la_data_in[44]
la_data_in[45]
la_data_in[46]
la_data_in[47]
la_data_in[4]
la_data_in[5]
la_data_in[66]
la_data_in[67]
la_data_in[68]
la_data_in[69]
la_data_in[6]
la_data_in[70]
la_data_in[71]
la_data_in[72]
la_data_in[73]
la_data_in[74]
la_data_in[75]
la_data_in[76]
la_data_in[77]
la_data_in[78]
la_data_in[79]
la_data_in[7]
la_data_in[80]
la_data_in[81]
la_data_in[82]
la_data_in[83]
la_data_in[84]
la_data_in[85]
la_data_in[86]
la_data_in[87]
la_data_in[88]
la_data_in[89]
la_data_in[8]
la_data_in[90]
la_data_in[91]
la_data_in[92]
la_data_in[93]
la_data_in[94]
la_data_in[95]
la_data_in[96]
la_data_in[97]
la_data_in[98]
la_data_in[99]
la_data_in[9]
la_oenb[0]
la_oenb[100]
la_oenb[101]
la_oenb[102]
la_oenb[103]
la_oenb[104]
la_oenb[105]
la_oenb[106]
la_oenb[107]
la_oenb[108]
la_oenb[109]
la_oenb[10]
la_oenb[110]
la_oenb[111]
la_oenb[112]
la_oenb[113]
la_oenb[114]
la_oenb[115]
la_oenb[116]
la_oenb[117]
la_oenb[118]
la_oenb[119]
la_oenb[11]
la_oenb[120]
la_oenb[121]
la_oenb[122]
la_oenb[123]
la_oenb[124]
la_oenb[125]
la_oenb[126]
la_oenb[127]
la_oenb[12]
la_oenb[13]
la_oenb[14]
la_oenb[15]
la_oenb[16]
la_oenb[17]
la_oenb[18]
la_oenb[19]
la_oenb[1]
la_oenb[20]
la_oenb[21]
la_oenb[22]
la_oenb[23]
la_oenb[24]
la_oenb[25]
la_oenb[26]
la_oenb[27]
la_oenb[28]
la_oenb[29]
la_oenb[2]
la_oenb[30]
la_oenb[31]
la_oenb[32]
la_oenb[33]
la_oenb[34]
la_oenb[35]
la_oenb[36]
la_oenb[37]
la_oenb[38]
la_oenb[39]
la_oenb[3]
la_oenb[40]
la_oenb[41]
la_oenb[42]
la_oenb[43]
la_oenb[44]
la_oenb[45]
la_oenb[46]
la_oenb[47]
la_oenb[4]
la_oenb[5]
la_oenb[66]
la_oenb[67]
la_oenb[68]
la_oenb[69]
la_oenb[6]
la_oenb[70]
la_oenb[71]
la_oenb[72]
la_oenb[73]
la_oenb[74]
la_oenb[75]
la_oenb[76]
la_oenb[77]
la_oenb[78]
la_oenb[79]
la_oenb[7]
la_oenb[80]
la_oenb[81]
la_oenb[82]
la_oenb[83]
la_oenb[84]
la_oenb[85]
la_oenb[86]
la_oenb[87]
la_oenb[88]
la_oenb[89]
la_oenb[8]
la_oenb[90]
la_oenb[91]
la_oenb[92]
la_oenb[93]
la_oenb[94]
la_oenb[95]
la_oenb[96]
la_oenb[97]
la_oenb[98]
la_oenb[99]
la_oenb[9]
wbs_adr_i[0]
wbs_adr_i[10]
wbs_adr_i[11]
wbs_adr_i[12]
wbs_adr_i[13]
wbs_adr_i[14]
wbs_adr_i[15]
wbs_adr_i[16]
wbs_adr_i[17]
wbs_adr_i[18]
wbs_adr_i[19]
wbs_adr_i[1]
wbs_adr_i[20]
wbs_adr_i[21]
wbs_adr_i[22]
wbs_adr_i[23]
wbs_adr_i[24]
wbs_adr_i[25]
wbs_adr_i[26]
wbs_adr_i[27]
wbs_adr_i[28]
wbs_adr_i[29]
wbs_adr_i[2]
wbs_adr_i[30]
wbs_adr_i[31]
wbs_adr_i[3]
wbs_adr_i[4]
wbs_adr_i[5]
wbs_adr_i[6]
wbs_adr_i[7]
wbs_adr_i[8]
wbs_adr_i[9]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_sel_i[2]
wbs_sel_i[3]
clkload0/X
clkload1/X
clkload2/X
user_proj_example_141/HI
user_proj_example_142/HI
user_proj_example_143/HI
user_proj_example_144/HI
user_proj_example_145/HI
user_proj_example_146/HI
user_proj_example_147/HI
user_proj_example_148/HI
user_proj_example_149/HI
user_proj_example_150/HI
user_proj_example_151/HI
user_proj_example_152/HI
user_proj_example_153/HI
user_proj_example_154/HI
user_proj_example_155/HI
user_proj_example_156/HI
user_proj_example_157/HI
user_proj_example_158/HI
user_proj_example_159/HI
user_proj_example_160/HI
user_proj_example_161/HI
user_proj_example_162/HI
user_proj_example_163/HI
user_proj_example_164/HI
user_proj_example_165/HI
user_proj_example_166/HI
user_proj_example_167/HI
user_proj_example_168/HI
user_proj_example_169/HI
user_proj_example_170/HI
user_proj_example_171/HI
user_proj_example_172/HI
user_proj_example_173/HI
user_proj_example_174/HI
user_proj_example_175/HI
user_proj_example_176/HI
user_proj_example_177/HI
user_proj_example_178/HI
user_proj_example_179/HI
user_proj_example_180/HI
user_proj_example_181/HI
user_proj_example_182/HI
user_proj_example_183/HI
user_proj_example_184/HI
user_proj_example_185/HI
user_proj_example_186/HI
user_proj_example_187/HI
user_proj_example_188/HI
user_proj_example_189/HI
user_proj_example_190/HI
user_proj_example_191/HI
user_proj_example_192/HI
user_proj_example_193/HI
user_proj_example_194/HI
user_proj_example_195/HI
user_proj_example_196/HI
user_proj_example_197/HI
user_proj_example_198/HI
user_proj_example_199/HI
user_proj_example_200/HI
user_proj_example_201/HI
user_proj_example_202/HI
user_proj_example_203/HI
user_proj_example_204/HI
user_proj_example_205/HI
user_proj_example_206/HI
user_proj_example_207/HI
user_proj_example_208/HI
user_proj_example_209/HI
user_proj_example_210/HI
user_proj_example_211/HI
user_proj_example_212/HI
user_proj_example_213/HI
user_proj_example_214/HI
user_proj_example_215/HI
user_proj_example_216/HI
user_proj_example_217/HI
user_proj_example_218/HI
user_proj_example_219/HI
user_proj_example_220/HI
user_proj_example_221/HI
user_proj_example_222/HI
user_proj_example_223/HI
user_proj_example_224/HI
user_proj_example_225/HI
user_proj_example_226/HI
user_proj_example_227/HI
user_proj_example_228/HI
user_proj_example_229/HI
user_proj_example_230/HI
user_proj_example_231/HI
user_proj_example_232/HI
user_proj_example_233/HI
user_proj_example_234/HI
user_proj_example_235/HI
user_proj_example_236/HI
user_proj_example_237/HI
user_proj_example_238/HI
user_proj_example_239/HI
user_proj_example_240/HI
user_proj_example_241/HI
user_proj_example_242/HI
user_proj_example_243/HI
user_proj_example_244/HI
user_proj_example_245/HI
user_proj_example_246/HI
user_proj_example_247/HI
user_proj_example_248/HI
user_proj_example_249/HI
user_proj_example_250/HI
user_proj_example_251/HI
user_proj_example_252/HI
user_proj_example_253/HI
user_proj_example_254/HI
user_proj_example_255/HI
user_proj_example_256/HI
user_proj_example_257/HI
user_proj_example_258/HI
user_proj_example_259/HI
user_proj_example_260/HI
user_proj_example_261/HI
user_proj_example_262/HI
user_proj_example_263/HI
user_proj_example_264/HI
user_proj_example_265/HI
user_proj_example_266/HI
user_proj_example_267/HI
user_proj_example_268/HI
user_proj_example_269/HI
user_proj_example_270/HI
user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 120
max fanout violation count 14
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 16 input ports missing set_input_delay.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
Warning: There are 163 unconstrained endpoints.
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[1]
io_oeb[2]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[1]
io_out[2]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
irq[0]
irq[1]
irq[2]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

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@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
7.500853 network latency _328_/CLK
10.471798 network latency _305_/CLK
---------------
12.150853 16.041798 latency
3.890944 skew
rise -> fall
min max
4.650000 5.570000 source latency
7.592555 network latency _328_/CLK
10.682230 network latency _305_/CLK
---------------
12.242556 16.252230 latency
4.009675 skew
fall -> fall
min max
4.650000 5.570000 source latency
7.865334 network latency _328_/CLK
8.795438 network latency _305_/CLK
---------------
12.515333 14.365438 latency
1.850104 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 10.63 fmax = 94.10

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@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 2.904808e-05 2.633182e-05 5.104404e-07 5.589034e-05 13.6%
Combinational 8.197700e-05 2.071392e-04 3.839341e-06 2.929556e-04 71.1%
Clock 2.461694e-05 3.840392e-05 1.530292e-07 6.317389e-05 15.3%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.356420e-04 2.718751e-04 4.502832e-06 4.120198e-04 100.0%
32.9% 66.0% 1.1%

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@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
Clock clk
10.471774 source latency _296_/CLK ^
-7.684682 target latency _328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.037091 setup skew

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@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
Clock clk
7.690244 source latency _306_/CLK ^
-8.615106 target latency _312_/CLK ^
-0.250000 clock uncertainty
-0.920389 CRPR
--------------
-2.095250 hold skew

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@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
min_ss_100C_1v60: 0.0

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@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
min_ss_100C_1v60: 0.0

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@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
min_ss_100C_1v60: 0.0

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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
min_ss_100C_1v60: 0

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@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
min_ss_100C_1v60: 2.494424293279187

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
min_ss_100C_1v60: 1.141694771038144

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@@ -0,0 +1,746 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= min_tt_025C_1v80 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: _305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 ^ input external delay
2 0.004944 0.000000 0.000000 18.070000 ^ wb_rst_i (in)
wb_rst_i (net)
0.000055 0.000027 18.070026 ^ input37/A (sky130_fd_sc_hd__buf_4)
3 0.099660 0.276826 0.248036 18.318062 ^ input37/X (sky130_fd_sc_hd__buf_4)
net37 (net)
0.281453 0.028603 18.346664 ^ _153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.004837 0.066353 0.083247 18.429913 v _153_/Y (sky130_fd_sc_hd__a21oi_4)
_039_ (net)
0.066353 0.000092 18.430004 v hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004397 0.060437 0.569262 18.999268 v hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
net324 (net)
0.060437 0.000078 18.999346 v hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.056936 0.288685 0.785850 19.785194 v hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
net282 (net)
0.288693 0.001723 19.786917 v hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.040279 0.215661 0.826933 20.613852 v hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
net325 (net)
0.215661 0.000512 20.614363 v _160_/A (sky130_fd_sc_hd__nand2_2)
2 0.014904 0.105932 0.163373 20.777735 ^ _160_/Y (sky130_fd_sc_hd__nand2_2)
_044_ (net)
0.105936 0.000773 20.778509 ^ hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.045784 0.449853 0.847871 21.626379 ^ hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
net326 (net)
0.449853 0.001377 21.627756 ^ fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.132205 0.264068 0.320350 21.948107 ^ fanout124/X (sky130_fd_sc_hd__buf_6)
net124 (net)
0.264072 0.000833 21.948938 ^ _161_/A (sky130_fd_sc_hd__inv_2)
2 0.006861 0.057027 0.065860 22.014799 v _161_/Y (sky130_fd_sc_hd__inv_2)
_000_ (net)
0.057027 0.000046 22.014845 v _233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002196 0.038286 0.238582 22.253428 v _233_/X (sky130_fd_sc_hd__a32o_1)
_009_ (net)
0.038286 0.000012 22.253441 v hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002146 0.049763 0.539636 22.793077 v hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
net431 (net)
0.049763 0.000021 22.793098 v hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002636 0.051992 0.548550 23.341648 v hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
net315 (net)
0.051992 0.000030 23.341679 v hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.001933 0.048629 0.543027 23.884705 v hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
net432 (net)
0.048629 0.000018 23.884722 v _305_/D (sky130_fd_sc_hd__dfxtp_4)
23.884722 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.029311 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.615171 0.002586 29.652586 ^ wire3/A (sky130_fd_sc_hd__buf_4)
3 0.043704 0.132262 0.295431 29.948017 ^ wire3/X (sky130_fd_sc_hd__buf_4)
net274 (net)
0.132669 0.005294 29.953310 ^ wire2/A (sky130_fd_sc_hd__buf_6)
3 0.098359 0.197490 0.236508 30.189817 ^ wire2/X (sky130_fd_sc_hd__buf_6)
net273 (net)
0.197760 0.006004 30.195822 ^ _155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.049934 0.437838 0.451490 30.647312 ^ _155_/X (sky130_fd_sc_hd__mux2_1)
clk (net)
0.437849 0.001894 30.649204 ^ wire1/A (sky130_fd_sc_hd__buf_4)
3 0.046619 0.138052 0.273211 30.922415 ^ wire1/X (sky130_fd_sc_hd__buf_4)
net272 (net)
0.138379 0.005464 30.927879 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.090763 0.107644 0.211031 31.138910 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_0_clk (net)
0.107883 0.004100 31.143011 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.062247 0.080381 0.180286 31.323298 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_2_2__leaf_clk (net)
0.080802 0.004576 31.327873 ^ _305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 31.077871 clock uncertainty
0.000000 31.077871 clock reconvergence pessimism
-0.105396 30.972477 library setup time
30.972477 data required time
---------------------------------------------------------------------------------------------
30.972477 data required time
-23.884722 data arrival time
---------------------------------------------------------------------------------------------
7.087755 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
fanout124/X 16 33 -17 (VIOLATED)
fanout125/X 16 33 -17 (VIOLATED)
_159_/Y 16 29 -13 (VIOLATED)
_156_/X 16 27 -11 (VIOLATED)
_195_/X 16 23 -7 (VIOLATED)
_182_/X 16 21 -5 (VIOLATED)
clkbuf_2_2__f_clk/X 16 21 -5 (VIOLATED)
_176_/Y 16 19 -3 (VIOLATED)
_297_/Q 16 19 -3 (VIOLATED)
clkbuf_2_1__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_3__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_0__f_clk/X 16 17 (VIOLATED)
hold140/X 16 17 (VIOLATED)
wire4/X 16 17 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 420 unannotated drivers.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
la_data_in[0]
la_data_in[100]
la_data_in[101]
la_data_in[102]
la_data_in[103]
la_data_in[104]
la_data_in[105]
la_data_in[106]
la_data_in[107]
la_data_in[108]
la_data_in[109]
la_data_in[10]
la_data_in[110]
la_data_in[111]
la_data_in[112]
la_data_in[113]
la_data_in[114]
la_data_in[115]
la_data_in[116]
la_data_in[117]
la_data_in[118]
la_data_in[119]
la_data_in[11]
la_data_in[120]
la_data_in[121]
la_data_in[122]
la_data_in[123]
la_data_in[124]
la_data_in[125]
la_data_in[126]
la_data_in[127]
la_data_in[12]
la_data_in[13]
la_data_in[14]
la_data_in[15]
la_data_in[16]
la_data_in[17]
la_data_in[18]
la_data_in[19]
la_data_in[1]
la_data_in[20]
la_data_in[21]
la_data_in[22]
la_data_in[23]
la_data_in[24]
la_data_in[25]
la_data_in[26]
la_data_in[27]
la_data_in[28]
la_data_in[29]
la_data_in[2]
la_data_in[30]
la_data_in[31]
la_data_in[32]
la_data_in[33]
la_data_in[34]
la_data_in[35]
la_data_in[36]
la_data_in[37]
la_data_in[38]
la_data_in[39]
la_data_in[3]
la_data_in[40]
la_data_in[41]
la_data_in[42]
la_data_in[43]
la_data_in[44]
la_data_in[45]
la_data_in[46]
la_data_in[47]
la_data_in[4]
la_data_in[5]
la_data_in[66]
la_data_in[67]
la_data_in[68]
la_data_in[69]
la_data_in[6]
la_data_in[70]
la_data_in[71]
la_data_in[72]
la_data_in[73]
la_data_in[74]
la_data_in[75]
la_data_in[76]
la_data_in[77]
la_data_in[78]
la_data_in[79]
la_data_in[7]
la_data_in[80]
la_data_in[81]
la_data_in[82]
la_data_in[83]
la_data_in[84]
la_data_in[85]
la_data_in[86]
la_data_in[87]
la_data_in[88]
la_data_in[89]
la_data_in[8]
la_data_in[90]
la_data_in[91]
la_data_in[92]
la_data_in[93]
la_data_in[94]
la_data_in[95]
la_data_in[96]
la_data_in[97]
la_data_in[98]
la_data_in[99]
la_data_in[9]
la_oenb[0]
la_oenb[100]
la_oenb[101]
la_oenb[102]
la_oenb[103]
la_oenb[104]
la_oenb[105]
la_oenb[106]
la_oenb[107]
la_oenb[108]
la_oenb[109]
la_oenb[10]
la_oenb[110]
la_oenb[111]
la_oenb[112]
la_oenb[113]
la_oenb[114]
la_oenb[115]
la_oenb[116]
la_oenb[117]
la_oenb[118]
la_oenb[119]
la_oenb[11]
la_oenb[120]
la_oenb[121]
la_oenb[122]
la_oenb[123]
la_oenb[124]
la_oenb[125]
la_oenb[126]
la_oenb[127]
la_oenb[12]
la_oenb[13]
la_oenb[14]
la_oenb[15]
la_oenb[16]
la_oenb[17]
la_oenb[18]
la_oenb[19]
la_oenb[1]
la_oenb[20]
la_oenb[21]
la_oenb[22]
la_oenb[23]
la_oenb[24]
la_oenb[25]
la_oenb[26]
la_oenb[27]
la_oenb[28]
la_oenb[29]
la_oenb[2]
la_oenb[30]
la_oenb[31]
la_oenb[32]
la_oenb[33]
la_oenb[34]
la_oenb[35]
la_oenb[36]
la_oenb[37]
la_oenb[38]
la_oenb[39]
la_oenb[3]
la_oenb[40]
la_oenb[41]
la_oenb[42]
la_oenb[43]
la_oenb[44]
la_oenb[45]
la_oenb[46]
la_oenb[47]
la_oenb[4]
la_oenb[5]
la_oenb[66]
la_oenb[67]
la_oenb[68]
la_oenb[69]
la_oenb[6]
la_oenb[70]
la_oenb[71]
la_oenb[72]
la_oenb[73]
la_oenb[74]
la_oenb[75]
la_oenb[76]
la_oenb[77]
la_oenb[78]
la_oenb[79]
la_oenb[7]
la_oenb[80]
la_oenb[81]
la_oenb[82]
la_oenb[83]
la_oenb[84]
la_oenb[85]
la_oenb[86]
la_oenb[87]
la_oenb[88]
la_oenb[89]
la_oenb[8]
la_oenb[90]
la_oenb[91]
la_oenb[92]
la_oenb[93]
la_oenb[94]
la_oenb[95]
la_oenb[96]
la_oenb[97]
la_oenb[98]
la_oenb[99]
la_oenb[9]
wbs_adr_i[0]
wbs_adr_i[10]
wbs_adr_i[11]
wbs_adr_i[12]
wbs_adr_i[13]
wbs_adr_i[14]
wbs_adr_i[15]
wbs_adr_i[16]
wbs_adr_i[17]
wbs_adr_i[18]
wbs_adr_i[19]
wbs_adr_i[1]
wbs_adr_i[20]
wbs_adr_i[21]
wbs_adr_i[22]
wbs_adr_i[23]
wbs_adr_i[24]
wbs_adr_i[25]
wbs_adr_i[26]
wbs_adr_i[27]
wbs_adr_i[28]
wbs_adr_i[29]
wbs_adr_i[2]
wbs_adr_i[30]
wbs_adr_i[31]
wbs_adr_i[3]
wbs_adr_i[4]
wbs_adr_i[5]
wbs_adr_i[6]
wbs_adr_i[7]
wbs_adr_i[8]
wbs_adr_i[9]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_sel_i[2]
wbs_sel_i[3]
clkload0/X
clkload1/X
clkload2/X
user_proj_example_141/HI
user_proj_example_142/HI
user_proj_example_143/HI
user_proj_example_144/HI
user_proj_example_145/HI
user_proj_example_146/HI
user_proj_example_147/HI
user_proj_example_148/HI
user_proj_example_149/HI
user_proj_example_150/HI
user_proj_example_151/HI
user_proj_example_152/HI
user_proj_example_153/HI
user_proj_example_154/HI
user_proj_example_155/HI
user_proj_example_156/HI
user_proj_example_157/HI
user_proj_example_158/HI
user_proj_example_159/HI
user_proj_example_160/HI
user_proj_example_161/HI
user_proj_example_162/HI
user_proj_example_163/HI
user_proj_example_164/HI
user_proj_example_165/HI
user_proj_example_166/HI
user_proj_example_167/HI
user_proj_example_168/HI
user_proj_example_169/HI
user_proj_example_170/HI
user_proj_example_171/HI
user_proj_example_172/HI
user_proj_example_173/HI
user_proj_example_174/HI
user_proj_example_175/HI
user_proj_example_176/HI
user_proj_example_177/HI
user_proj_example_178/HI
user_proj_example_179/HI
user_proj_example_180/HI
user_proj_example_181/HI
user_proj_example_182/HI
user_proj_example_183/HI
user_proj_example_184/HI
user_proj_example_185/HI
user_proj_example_186/HI
user_proj_example_187/HI
user_proj_example_188/HI
user_proj_example_189/HI
user_proj_example_190/HI
user_proj_example_191/HI
user_proj_example_192/HI
user_proj_example_193/HI
user_proj_example_194/HI
user_proj_example_195/HI
user_proj_example_196/HI
user_proj_example_197/HI
user_proj_example_198/HI
user_proj_example_199/HI
user_proj_example_200/HI
user_proj_example_201/HI
user_proj_example_202/HI
user_proj_example_203/HI
user_proj_example_204/HI
user_proj_example_205/HI
user_proj_example_206/HI
user_proj_example_207/HI
user_proj_example_208/HI
user_proj_example_209/HI
user_proj_example_210/HI
user_proj_example_211/HI
user_proj_example_212/HI
user_proj_example_213/HI
user_proj_example_214/HI
user_proj_example_215/HI
user_proj_example_216/HI
user_proj_example_217/HI
user_proj_example_218/HI
user_proj_example_219/HI
user_proj_example_220/HI
user_proj_example_221/HI
user_proj_example_222/HI
user_proj_example_223/HI
user_proj_example_224/HI
user_proj_example_225/HI
user_proj_example_226/HI
user_proj_example_227/HI
user_proj_example_228/HI
user_proj_example_229/HI
user_proj_example_230/HI
user_proj_example_231/HI
user_proj_example_232/HI
user_proj_example_233/HI
user_proj_example_234/HI
user_proj_example_235/HI
user_proj_example_236/HI
user_proj_example_237/HI
user_proj_example_238/HI
user_proj_example_239/HI
user_proj_example_240/HI
user_proj_example_241/HI
user_proj_example_242/HI
user_proj_example_243/HI
user_proj_example_244/HI
user_proj_example_245/HI
user_proj_example_246/HI
user_proj_example_247/HI
user_proj_example_248/HI
user_proj_example_249/HI
user_proj_example_250/HI
user_proj_example_251/HI
user_proj_example_252/HI
user_proj_example_253/HI
user_proj_example_254/HI
user_proj_example_255/HI
user_proj_example_256/HI
user_proj_example_257/HI
user_proj_example_258/HI
user_proj_example_259/HI
user_proj_example_260/HI
user_proj_example_261/HI
user_proj_example_262/HI
user_proj_example_263/HI
user_proj_example_264/HI
user_proj_example_265/HI
user_proj_example_266/HI
user_proj_example_267/HI
user_proj_example_268/HI
user_proj_example_269/HI
user_proj_example_270/HI
user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 14
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 16 input ports missing set_input_delay.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
Warning: There are 163 unconstrained endpoints.
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[1]
io_oeb[2]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[1]
io_out[2]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
irq[0]
irq[1]
irq[2]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

View File

@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
6.310304 network latency _328_/CLK
9.235803 network latency _305_/CLK
---------------
10.960304 14.805803 latency
3.845499 skew
rise -> fall
min max
4.650000 5.570000 source latency
6.292112 network latency _328_/CLK
9.247493 network latency _305_/CLK
---------------
10.942112 14.817493 latency
3.875382 skew
fall -> fall
min max
4.650000 5.570000 source latency
6.432544 network latency _328_/CLK
7.360063 network latency _305_/CLK
---------------
11.082543 12.930062 latency
1.847520 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 5.39 fmax = 185.54

View File

@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 3.690075e-05 3.338997e-05 2.838373e-10 7.029100e-05 13.7%
Combinational 1.018172e-04 2.622666e-04 3.073229e-09 3.640869e-04 71.0%
Clock 3.011071e-05 4.853097e-05 4.242312e-09 7.864592e-05 15.3%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.688287e-04 3.441875e-04 7.599371e-09 5.130239e-04 100.0%
32.9% 67.1% 0.0%

View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
Clock clk
9.235778 source latency _296_/CLK ^
-6.319011 target latency _328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.166766 setup skew

View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
Clock clk
6.322192 source latency _306_/CLK ^
-7.246746 target latency _312_/CLK ^
-0.250000 clock uncertainty
-0.920073 CRPR
--------------
-2.094627 hold skew

View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
min_tt_025C_1v80: 0.0

View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
min_tt_025C_1v80: 0.0

View File

@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
min_tt_025C_1v80: 0.0

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
min_tt_025C_1v80: 0

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
min_tt_025C_1v80: 7.087754583861198

View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
min_tt_025C_1v80: 0.4132969639063154

View File

@@ -0,0 +1,746 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= nom_ff_n40C_1v95 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: _305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 v input external delay
2 0.004723 0.000000 0.000000 18.070000 v wb_rst_i (in)
wb_rst_i (net)
0.000092 0.000046 18.070045 v input37/A (sky130_fd_sc_hd__buf_4)
3 0.108655 0.098498 0.130852 18.200897 v input37/X (sky130_fd_sc_hd__buf_4)
net37 (net)
0.121183 0.035705 18.236603 v _153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005545 0.074996 0.111346 18.347948 ^ _153_/Y (sky130_fd_sc_hd__a21oi_4)
_039_ (net)
0.074996 0.000217 18.348164 ^ hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.005025 0.052293 0.391914 18.740078 ^ hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
net324 (net)
0.052293 0.000187 18.740265 ^ hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.062476 0.466357 0.679625 19.419889 ^ hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
net282 (net)
0.466371 0.003160 19.423050 ^ hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.044214 0.333547 0.610321 20.033371 ^ hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
net325 (net)
0.333547 0.001027 20.034397 ^ _160_/A (sky130_fd_sc_hd__nand2_2)
2 0.015898 0.097801 0.069653 20.104050 v _160_/Y (sky130_fd_sc_hd__nand2_2)
_044_ (net)
0.097825 0.001162 20.105213 v hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.049252 0.177382 0.526864 20.632076 v hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
net326 (net)
0.177413 0.002304 20.634380 v fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.135384 0.088000 0.178170 20.812550 v fanout124/X (sky130_fd_sc_hd__buf_6)
net124 (net)
0.088060 0.002332 20.814882 v _161_/A (sky130_fd_sc_hd__inv_2)
2 0.007691 0.040591 0.060174 20.875057 ^ _161_/Y (sky130_fd_sc_hd__inv_2)
_000_ (net)
0.040591 0.000158 20.875216 ^ _233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002556 0.036373 0.083707 20.958921 ^ _233_/X (sky130_fd_sc_hd__a32o_1)
_009_ (net)
0.036373 0.000053 20.958975 ^ hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002501 0.035526 0.370010 21.328985 ^ hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
net431 (net)
0.035526 0.000075 21.329060 ^ hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.003063 0.039009 0.373420 21.702480 ^ hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
net315 (net)
0.039009 0.000098 21.702578 ^ hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002147 0.033551 0.368312 22.070890 ^ hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
net432 (net)
0.033551 0.000062 22.070951 ^ _305_/D (sky130_fd_sc_hd__dfxtp_4)
22.070951 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.031295 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.616706 0.003354 29.653353 ^ wire3/A (sky130_fd_sc_hd__buf_4)
3 0.047494 0.108368 0.156264 29.809616 ^ wire3/X (sky130_fd_sc_hd__buf_4)
net274 (net)
0.109169 0.007411 29.817028 ^ wire2/A (sky130_fd_sc_hd__buf_6)
3 0.110721 0.166913 0.170463 29.987492 ^ wire2/X (sky130_fd_sc_hd__buf_6)
net273 (net)
0.167766 0.009710 29.997200 ^ _155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.054209 0.356656 0.328015 30.325214 ^ _155_/X (sky130_fd_sc_hd__mux2_1)
clk (net)
0.356703 0.003464 30.328680 ^ wire1/A (sky130_fd_sc_hd__buf_4)
3 0.051279 0.112790 0.161343 30.490023 ^ wire1/X (sky130_fd_sc_hd__buf_4)
net272 (net)
0.113608 0.007699 30.497721 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.096415 0.086814 0.147828 30.645550 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_0_clk (net)
0.087448 0.005915 30.651464 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.066435 0.064390 0.124832 30.776297 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
clknet_2_2__leaf_clk (net)
0.065768 0.007393 30.783689 ^ _305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 30.533688 clock uncertainty
0.000000 30.533688 clock reconvergence pessimism
-0.030788 30.502901 library setup time
30.502901 data required time
---------------------------------------------------------------------------------------------
30.502901 data required time
-22.070951 data arrival time
---------------------------------------------------------------------------------------------
8.431949 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= nom_ff_n40C_1v95 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= nom_ff_n40C_1v95 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
fanout124/X 16 33 -17 (VIOLATED)
fanout125/X 16 33 -17 (VIOLATED)
_159_/Y 16 29 -13 (VIOLATED)
_156_/X 16 27 -11 (VIOLATED)
_195_/X 16 23 -7 (VIOLATED)
_182_/X 16 21 -5 (VIOLATED)
clkbuf_2_2__f_clk/X 16 21 -5 (VIOLATED)
_176_/Y 16 19 -3 (VIOLATED)
_297_/Q 16 19 -3 (VIOLATED)
clkbuf_2_1__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_3__f_clk/X 16 19 -3 (VIOLATED)
clkbuf_2_0__f_clk/X 16 17 (VIOLATED)
hold140/X 16 17 (VIOLATED)
wire4/X 16 17 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 420 unannotated drivers.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
la_data_in[0]
la_data_in[100]
la_data_in[101]
la_data_in[102]
la_data_in[103]
la_data_in[104]
la_data_in[105]
la_data_in[106]
la_data_in[107]
la_data_in[108]
la_data_in[109]
la_data_in[10]
la_data_in[110]
la_data_in[111]
la_data_in[112]
la_data_in[113]
la_data_in[114]
la_data_in[115]
la_data_in[116]
la_data_in[117]
la_data_in[118]
la_data_in[119]
la_data_in[11]
la_data_in[120]
la_data_in[121]
la_data_in[122]
la_data_in[123]
la_data_in[124]
la_data_in[125]
la_data_in[126]
la_data_in[127]
la_data_in[12]
la_data_in[13]
la_data_in[14]
la_data_in[15]
la_data_in[16]
la_data_in[17]
la_data_in[18]
la_data_in[19]
la_data_in[1]
la_data_in[20]
la_data_in[21]
la_data_in[22]
la_data_in[23]
la_data_in[24]
la_data_in[25]
la_data_in[26]
la_data_in[27]
la_data_in[28]
la_data_in[29]
la_data_in[2]
la_data_in[30]
la_data_in[31]
la_data_in[32]
la_data_in[33]
la_data_in[34]
la_data_in[35]
la_data_in[36]
la_data_in[37]
la_data_in[38]
la_data_in[39]
la_data_in[3]
la_data_in[40]
la_data_in[41]
la_data_in[42]
la_data_in[43]
la_data_in[44]
la_data_in[45]
la_data_in[46]
la_data_in[47]
la_data_in[4]
la_data_in[5]
la_data_in[66]
la_data_in[67]
la_data_in[68]
la_data_in[69]
la_data_in[6]
la_data_in[70]
la_data_in[71]
la_data_in[72]
la_data_in[73]
la_data_in[74]
la_data_in[75]
la_data_in[76]
la_data_in[77]
la_data_in[78]
la_data_in[79]
la_data_in[7]
la_data_in[80]
la_data_in[81]
la_data_in[82]
la_data_in[83]
la_data_in[84]
la_data_in[85]
la_data_in[86]
la_data_in[87]
la_data_in[88]
la_data_in[89]
la_data_in[8]
la_data_in[90]
la_data_in[91]
la_data_in[92]
la_data_in[93]
la_data_in[94]
la_data_in[95]
la_data_in[96]
la_data_in[97]
la_data_in[98]
la_data_in[99]
la_data_in[9]
la_oenb[0]
la_oenb[100]
la_oenb[101]
la_oenb[102]
la_oenb[103]
la_oenb[104]
la_oenb[105]
la_oenb[106]
la_oenb[107]
la_oenb[108]
la_oenb[109]
la_oenb[10]
la_oenb[110]
la_oenb[111]
la_oenb[112]
la_oenb[113]
la_oenb[114]
la_oenb[115]
la_oenb[116]
la_oenb[117]
la_oenb[118]
la_oenb[119]
la_oenb[11]
la_oenb[120]
la_oenb[121]
la_oenb[122]
la_oenb[123]
la_oenb[124]
la_oenb[125]
la_oenb[126]
la_oenb[127]
la_oenb[12]
la_oenb[13]
la_oenb[14]
la_oenb[15]
la_oenb[16]
la_oenb[17]
la_oenb[18]
la_oenb[19]
la_oenb[1]
la_oenb[20]
la_oenb[21]
la_oenb[22]
la_oenb[23]
la_oenb[24]
la_oenb[25]
la_oenb[26]
la_oenb[27]
la_oenb[28]
la_oenb[29]
la_oenb[2]
la_oenb[30]
la_oenb[31]
la_oenb[32]
la_oenb[33]
la_oenb[34]
la_oenb[35]
la_oenb[36]
la_oenb[37]
la_oenb[38]
la_oenb[39]
la_oenb[3]
la_oenb[40]
la_oenb[41]
la_oenb[42]
la_oenb[43]
la_oenb[44]
la_oenb[45]
la_oenb[46]
la_oenb[47]
la_oenb[4]
la_oenb[5]
la_oenb[66]
la_oenb[67]
la_oenb[68]
la_oenb[69]
la_oenb[6]
la_oenb[70]
la_oenb[71]
la_oenb[72]
la_oenb[73]
la_oenb[74]
la_oenb[75]
la_oenb[76]
la_oenb[77]
la_oenb[78]
la_oenb[79]
la_oenb[7]
la_oenb[80]
la_oenb[81]
la_oenb[82]
la_oenb[83]
la_oenb[84]
la_oenb[85]
la_oenb[86]
la_oenb[87]
la_oenb[88]
la_oenb[89]
la_oenb[8]
la_oenb[90]
la_oenb[91]
la_oenb[92]
la_oenb[93]
la_oenb[94]
la_oenb[95]
la_oenb[96]
la_oenb[97]
la_oenb[98]
la_oenb[99]
la_oenb[9]
wbs_adr_i[0]
wbs_adr_i[10]
wbs_adr_i[11]
wbs_adr_i[12]
wbs_adr_i[13]
wbs_adr_i[14]
wbs_adr_i[15]
wbs_adr_i[16]
wbs_adr_i[17]
wbs_adr_i[18]
wbs_adr_i[19]
wbs_adr_i[1]
wbs_adr_i[20]
wbs_adr_i[21]
wbs_adr_i[22]
wbs_adr_i[23]
wbs_adr_i[24]
wbs_adr_i[25]
wbs_adr_i[26]
wbs_adr_i[27]
wbs_adr_i[28]
wbs_adr_i[29]
wbs_adr_i[2]
wbs_adr_i[30]
wbs_adr_i[31]
wbs_adr_i[3]
wbs_adr_i[4]
wbs_adr_i[5]
wbs_adr_i[6]
wbs_adr_i[7]
wbs_adr_i[8]
wbs_adr_i[9]
wbs_dat_i[16]
wbs_dat_i[17]
wbs_dat_i[18]
wbs_dat_i[19]
wbs_dat_i[20]
wbs_dat_i[21]
wbs_dat_i[22]
wbs_dat_i[23]
wbs_dat_i[24]
wbs_dat_i[25]
wbs_dat_i[26]
wbs_dat_i[27]
wbs_dat_i[28]
wbs_dat_i[29]
wbs_dat_i[30]
wbs_dat_i[31]
wbs_sel_i[2]
wbs_sel_i[3]
clkload0/X
clkload1/X
clkload2/X
user_proj_example_141/HI
user_proj_example_142/HI
user_proj_example_143/HI
user_proj_example_144/HI
user_proj_example_145/HI
user_proj_example_146/HI
user_proj_example_147/HI
user_proj_example_148/HI
user_proj_example_149/HI
user_proj_example_150/HI
user_proj_example_151/HI
user_proj_example_152/HI
user_proj_example_153/HI
user_proj_example_154/HI
user_proj_example_155/HI
user_proj_example_156/HI
user_proj_example_157/HI
user_proj_example_158/HI
user_proj_example_159/HI
user_proj_example_160/HI
user_proj_example_161/HI
user_proj_example_162/HI
user_proj_example_163/HI
user_proj_example_164/HI
user_proj_example_165/HI
user_proj_example_166/HI
user_proj_example_167/HI
user_proj_example_168/HI
user_proj_example_169/HI
user_proj_example_170/HI
user_proj_example_171/HI
user_proj_example_172/HI
user_proj_example_173/HI
user_proj_example_174/HI
user_proj_example_175/HI
user_proj_example_176/HI
user_proj_example_177/HI
user_proj_example_178/HI
user_proj_example_179/HI
user_proj_example_180/HI
user_proj_example_181/HI
user_proj_example_182/HI
user_proj_example_183/HI
user_proj_example_184/HI
user_proj_example_185/HI
user_proj_example_186/HI
user_proj_example_187/HI
user_proj_example_188/HI
user_proj_example_189/HI
user_proj_example_190/HI
user_proj_example_191/HI
user_proj_example_192/HI
user_proj_example_193/HI
user_proj_example_194/HI
user_proj_example_195/HI
user_proj_example_196/HI
user_proj_example_197/HI
user_proj_example_198/HI
user_proj_example_199/HI
user_proj_example_200/HI
user_proj_example_201/HI
user_proj_example_202/HI
user_proj_example_203/HI
user_proj_example_204/HI
user_proj_example_205/HI
user_proj_example_206/HI
user_proj_example_207/HI
user_proj_example_208/HI
user_proj_example_209/HI
user_proj_example_210/HI
user_proj_example_211/HI
user_proj_example_212/HI
user_proj_example_213/HI
user_proj_example_214/HI
user_proj_example_215/HI
user_proj_example_216/HI
user_proj_example_217/HI
user_proj_example_218/HI
user_proj_example_219/HI
user_proj_example_220/HI
user_proj_example_221/HI
user_proj_example_222/HI
user_proj_example_223/HI
user_proj_example_224/HI
user_proj_example_225/HI
user_proj_example_226/HI
user_proj_example_227/HI
user_proj_example_228/HI
user_proj_example_229/HI
user_proj_example_230/HI
user_proj_example_231/HI
user_proj_example_232/HI
user_proj_example_233/HI
user_proj_example_234/HI
user_proj_example_235/HI
user_proj_example_236/HI
user_proj_example_237/HI
user_proj_example_238/HI
user_proj_example_239/HI
user_proj_example_240/HI
user_proj_example_241/HI
user_proj_example_242/HI
user_proj_example_243/HI
user_proj_example_244/HI
user_proj_example_245/HI
user_proj_example_246/HI
user_proj_example_247/HI
user_proj_example_248/HI
user_proj_example_249/HI
user_proj_example_250/HI
user_proj_example_251/HI
user_proj_example_252/HI
user_proj_example_253/HI
user_proj_example_254/HI
user_proj_example_255/HI
user_proj_example_256/HI
user_proj_example_257/HI
user_proj_example_258/HI
user_proj_example_259/HI
user_proj_example_260/HI
user_proj_example_261/HI
user_proj_example_262/HI
user_proj_example_263/HI
user_proj_example_264/HI
user_proj_example_265/HI
user_proj_example_266/HI
user_proj_example_267/HI
user_proj_example_268/HI
user_proj_example_269/HI
user_proj_example_270/HI
user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 14
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 16 input ports missing set_input_delay.
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[1]
io_in[2]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
Warning: There are 163 unconstrained endpoints.
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[1]
io_oeb[2]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[1]
io_out[2]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
irq[0]
irq[1]
irq[2]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

View File

@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
5.773796 network latency _328_/CLK
8.776527 network latency _305_/CLK
---------------
10.423797 14.346528 latency
3.922732 skew
rise -> fall
min max
4.650000 5.570000 source latency
5.860782 network latency _328_/CLK
8.763387 network latency _305_/CLK
---------------
10.510782 14.333386 latency
3.822605 skew
fall -> fall
min max
4.650000 5.570000 source latency
5.907524 network latency _328_/CLK
6.838498 network latency _305_/CLK
---------------
10.557523 12.408498 latency
1.850975 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 3.66 fmax = 273.11

View File

@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= nom_ff_n40C_1v95 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 4.249388e-05 4.233407e-05 7.394261e-10 8.482870e-05 13.7%
Combinational 1.182377e-04 3.182565e-04 1.315145e-08 4.365074e-04 70.7%
Clock 3.454628e-05 6.183211e-05 5.304953e-09 9.638370e-05 15.6%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.952780e-04 4.224226e-04 1.919599e-08 6.177198e-04 100.0%
31.6% 68.4% 0.0%

View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= nom_ff_n40C_1v95 Corner ===================================
Clock clk
8.776481 source latency _296_/CLK ^
-5.773796 target latency _328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.252685 setup skew

View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= nom_ff_n40C_1v95 Corner ===================================
Clock clk
5.776331 source latency _306_/CLK ^
-6.702794 target latency _312_/CLK ^
-0.250000 clock uncertainty
-0.920001 CRPR
--------------
-2.096463 hold skew

View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
nom_ff_n40C_1v95: 0.0

View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
nom_ff_n40C_1v95: 0.0

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