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This commit is contained in:
Corey Hahn
2026-02-23 20:42:11 -07:00
committed by GitHub
commit 2ba96a115d
462 changed files with 9166588 additions and 0 deletions
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4
signoff/user_project_wrapper/openlane-signoff/antenna_summary.rpt Normal file
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┏━━━━━━━┳━━━━━━━━━┳━━━━━━━━━━┳━━━━━┳━━━━━┳━━━━━━━┓
┃ P / R ┃ Partial ┃ Required ┃ Net ┃ Pin ┃ Layer ┃
┡━━━━━━━╇━━━━━━━━━╇━━━━━━━━━━╇━━━━━╇━━━━━╇━━━━━━━┩
└───────┴─────────┴──────────┴─────┴─────┴───────┘

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signoff/user_project_wrapper/openlane-signoff/drc.klayout.xml Normal file
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<!-- Despite the name, this is the Magic DRC report in KLayout format. -->
<?xml version='1.0' encoding='utf8'?>
<report-database><cells><cell><name>user_project_wrapper</name></cell></cells><categories></categories><items></items></report-database>

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signoff/user_project_wrapper/openlane-signoff/drc.rpt Normal file
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user_project_wrapper
----------------------------------------
[INFO] COUNT: 0
[INFO] Should be divided by 3 or 4

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signoff/user_project_wrapper/openlane-signoff/error.log Normal file
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signoff/user_project_wrapper/openlane-signoff/flow.log Normal file
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signoff/user_project_wrapper/openlane-signoff/klayout-drc.log Normal file
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signoff/user_project_wrapper/openlane-signoff/lvs.rpt Normal file
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signoff/user_project_wrapper/openlane-signoff/magic-drc.log Normal file
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Magic 8.3 revision 489 - Compiled on Thu Aug 22 13:45:15 UTC 2024.
Starting magic under Tcl interpreter
Using the terminal as the console.
Using NULL graphics device.
Processing system .magicrc file
Sourcing design .magicrc for technology sky130A ...
2 Magic internal units = 1 Lambda
Input style sky130(): scaleFactor=2, multiplier=2
The following types are not handled by extraction and will be treated as non-electrical types:
ubm
Scaled tech values by 2 / 1 to match internal grid scaling
Loading sky130A Device Generator Menu ...
Loading "/nix/store/pqxyc4xmydcs5adig47yyc29r3svp5nx-python3-3.11.9-env/lib/python3.11/site-packages/librelane/scripts/magic/wrapper.tcl" from command line.
Warning: Calma reading is not undoable! I hope that's OK.
Library written using GDS-II Release 3.0
Library name: user_project_wrapper
Reading "EZ_sky130_ef_sc_hd__decap_40_12".
Reading "EZ_sky130_fd_sc_hd__decap_3".
Reading "EZ_sky130_fd_sc_hd__fill_1".
Reading "EZ_sky130_fd_sc_hd__tapvpwrvgnd_1".
Reading "EZ_sky130_fd_sc_hd__fill_2".
Reading "EZ_sky130_fd_sc_hd__fill_4".
Reading "EZ_sky130_fd_sc_hd__buf_4".
Reading "EZ_sky130_fd_sc_hd__fill_8".
Reading "EZ_sky130_fd_sc_hd__diode_2".
Reading "EZ_sky130_fd_sc_hd__buf_12".
Reading "EZ_sky130_fd_sc_hd__clkbuf_8".
Reading "EZ_sky130_fd_sc_hd__dlygate4sd3_1".
Reading "EZ_sky130_fd_sc_hd__clkbuf_4".
Reading "EZ_sky130_fd_sc_hd__buf_2".
Reading "EZ_sky130_fd_sc_hd__dfxtp_1".
Reading "EZ_sky130_fd_sc_hd__mux2_1".
Reading "EZ_sky130_fd_sc_hd__dfxtp_2".
Reading "EZ_sky130_fd_sc_hd__conb_1".
Reading "EZ_sky130_fd_sc_hd__and2_4".
Reading "EZ_sky130_fd_sc_hd__and2_2".
Reading "EZ_sky130_fd_sc_hd__nand2_8".
Reading "EZ_sky130_fd_sc_hd__nor2_2".
Reading "EZ_sky130_fd_sc_hd__inv_2".
Reading "EZ_sky130_fd_sc_hd__buf_6".
Reading "EZ_sky130_fd_sc_hd__nand3b_4".
Reading "EZ_sky130_fd_sc_hd__a211o_1".
Reading "EZ_sky130_fd_sc_hd__nor2_1".
Reading "EZ_sky130_fd_sc_hd__and3_1".
Reading "EZ_sky130_fd_sc_hd__a21oi_4".
Reading "EZ_sky130_fd_sc_hd__and2b_1".
Reading "EZ_sky130_fd_sc_hd__buf_1".
Reading "EZ_sky130_fd_sc_hd__a22o_1".
Reading "EZ_sky130_fd_sc_hd__a31o_1".
Reading "EZ_sky130_fd_sc_hd__o21a_1".
Reading "EZ_sky130_fd_sc_hd__a221o_1".
Reading "EZ_sky130_fd_sc_hd__a32o_1".
Reading "EZ_sky130_fd_sc_hd__and2_1".
Reading "EZ_sky130_fd_sc_hd__nand2_1".
Reading "EZ_sky130_fd_sc_hd__o2bb2a_1".
Reading "EZ_sky130_fd_sc_hd__a21oi_1".
Reading "EZ_sky130_fd_sc_hd__o21ai_1".
Reading "EZ_sky130_fd_sc_hd__a32o_4".
Reading "EZ_sky130_fd_sc_hd__a21o_1".
Reading "EZ_sky130_fd_sc_hd__or3b_2".
Reading "EZ_sky130_fd_sc_hd__and2b_2".
Reading "EZ_sky130_fd_sc_hd__a31o_4".
Reading "EZ_sky130_fd_sc_hd__clkbuf_1".
Reading "EZ_sky130_fd_sc_hd__or3b_4".
Reading "EZ_sky130_fd_sc_hd__and4_1".
Reading "EZ_sky130_fd_sc_hd__a41o_4".
Reading "EZ_sky130_fd_sc_hd__and3b_4".
Reading "EZ_sky130_fd_sc_hd__buf_8".
Reading "EZ_sky130_fd_sc_hd__clkbuf_16".
Reading "EZ_sky130_fd_sc_hd__dfxtp_4".
Reading "EZ_sky130_fd_sc_hd__nor2_8".
Reading "EZ_sky130_fd_sc_hd__or2_1".
Reading "EZ_sky130_fd_sc_hd__o31a_1".
Reading "EZ_sky130_fd_sc_hd__o211a_1".
Reading "EZ_sky130_fd_sc_hd__o32a_1".
Reading "EZ_sky130_fd_sc_hd__a31oi_1".
Reading "EZ_sky130_fd_sc_hd__o31ai_1".
Reading "EZ_sky130_fd_sc_hd__o211ai_4".
Reading "EZ_sky130_fd_sc_hd__a41oi_4".
Reading "EZ_sky130_fd_sc_hd__and4_2".
Reading "EZ_sky130_fd_sc_hd__xor2_1".
Reading "EZ_sky130_fd_sc_hd__or2_2".
Reading "EZ_sky130_fd_sc_hd__nor2_4".
Reading "EZ_sky130_fd_sc_hd__or3_4".
Reading "EZ_sky130_fd_sc_hd__nand2_2".
Reading "EZ_sky130_fd_sc_hd__xnor2_1".
Reading "EZ_sky130_fd_sc_hd__and3b_1".
Reading "EZ_sky130_fd_sc_hd__a31o_2".
Reading "EZ_sky130_fd_sc_hd__a21bo_1".
Reading "EZ_sky130_fd_sc_hd__a21boi_1".
Reading "EZ_sky130_fd_sc_hd__nand2b_1".
Reading "EZ_sky130_fd_sc_hd__xnor2_2".
Reading "EZ_sky130_fd_sc_hd__nand4_2".
Reading "EZ_sky130_fd_sc_hd__a41o_1".
Reading "EZ_sky130_fd_sc_hd__and4_4".
Reading "EZ_sky130_fd_sc_hd__clkbuf_2".
Reading "user_proj_example".
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Reading "user_project_wrapper".
[INFO] Loading user_project_wrapper
DRC style is now "drc(full)"
Loading DRC CIF style.
No errors found.
[INFO] COUNT: 0
[INFO] Should be divided by 3 or 4
[INFO] DRC Checking DONE (/home/marwan/caravel_user_project/openlane/user_project_wrapper/runs/25_11_11_05_00/55-magic-drc/reports/drc_violations.magic.rpt)
[INFO] Saving mag view with DRC errors (/home/marwan/caravel_user_project/openlane/user_project_wrapper/runs/25_11_11_05_00/55-magic-drc/views/user_project_wrapper.drc.mag)
[INFO] Saved

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signoff/user_project_wrapper/openlane-signoff/netgen-lvs.log Normal file
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Netgen 1.5.278 compiled on Sun Sep 29 13:29:03 UTC 2024
Warning: netgen command 'format' use fully-qualified name '::netgen::format'
Warning: netgen command 'global' use fully-qualified name '::netgen::global'
Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice'...
Call to undefined subcircuit sky130_fd_pr__pfet_01v8_hvt
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__nfet_01v8
Creating placeholder cell definition.
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_20_12.spice'...
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_40_12.spice'...
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_60_12.spice'...
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_80_12.spice'...
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_12.spice'...
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_2.spice'...
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_4.spice'...
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__fill_8.spice'...
Reading SPICE netlist file '/home/marwan/caravel_user_project/dependencies/pdks/sky130A/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice'...
Call to undefined subcircuit sky130_fd_pr__res_generic_po
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__special_nfet_01v8
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__diode_pw2nd_05v5
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_pr__special_pfet_01v8_hvt
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_sc_hd__nand2_2
Creating placeholder cell definition.
Call to undefined subcircuit sky130_fd_sc_hd__nor2_2
Creating placeholder cell definition.
Warning: A case-insensitive file has been read and so the verilog file must be treated case-insensitive to match.
Creating placeholder cell definition for module user_proj_example.
Treating empty subcircuits as black-box cells
Generating JSON file result
Reading setup file /nix/store/pqxyc4xmydcs5adig47yyc29r3svp5nx-python3-3.11.9-env/lib/python3.11/site-packages/librelane/scripts/netgen/setup.tcl
Model sky130_fd_pr__res_generic_po pin 1 == 2
No property value found for device sky130_fd_pr__res_generic_po
No property mult found for device sky130_fd_pr__res_generic_po
Model sky130_fd_pr__nfet_01v8 pin 1 == 3
No property mult found for device sky130_fd_pr__nfet_01v8
No property sa found for device sky130_fd_pr__nfet_01v8
No property sb found for device sky130_fd_pr__nfet_01v8
No property sd found for device sky130_fd_pr__nfet_01v8
No property nf found for device sky130_fd_pr__nfet_01v8
No property nrd found for device sky130_fd_pr__nfet_01v8
No property nrs found for device sky130_fd_pr__nfet_01v8
No property area found for device sky130_fd_pr__nfet_01v8
No property perim found for device sky130_fd_pr__nfet_01v8
No property topography found for device sky130_fd_pr__nfet_01v8
Model sky130_fd_pr__pfet_01v8_hvt pin 1 == 3
No property mult found for device sky130_fd_pr__pfet_01v8_hvt
No property sa found for device sky130_fd_pr__pfet_01v8_hvt
No property sb found for device sky130_fd_pr__pfet_01v8_hvt
No property sd found for device sky130_fd_pr__pfet_01v8_hvt
No property nf found for device sky130_fd_pr__pfet_01v8_hvt
No property nrd found for device sky130_fd_pr__pfet_01v8_hvt
No property nrs found for device sky130_fd_pr__pfet_01v8_hvt
No property area found for device sky130_fd_pr__pfet_01v8_hvt
No property perim found for device sky130_fd_pr__pfet_01v8_hvt
No property topography found for device sky130_fd_pr__pfet_01v8_hvt
Model sky130_fd_pr__special_nfet_01v8 pin 1 == 3
No property as found for device sky130_fd_pr__special_nfet_01v8
No property ad found for device sky130_fd_pr__special_nfet_01v8
No property ps found for device sky130_fd_pr__special_nfet_01v8
No property pd found for device sky130_fd_pr__special_nfet_01v8
No property mult found for device sky130_fd_pr__special_nfet_01v8
No property sa found for device sky130_fd_pr__special_nfet_01v8
No property sb found for device sky130_fd_pr__special_nfet_01v8
No property sd found for device sky130_fd_pr__special_nfet_01v8
No property nf found for device sky130_fd_pr__special_nfet_01v8
No property nrd found for device sky130_fd_pr__special_nfet_01v8
No property nrs found for device sky130_fd_pr__special_nfet_01v8
No property area found for device sky130_fd_pr__special_nfet_01v8
No property perim found for device sky130_fd_pr__special_nfet_01v8
No property topography found for device sky130_fd_pr__special_nfet_01v8
Model sky130_fd_pr__special_pfet_01v8_hvt pin 1 == 3
No property as found for device sky130_fd_pr__special_pfet_01v8_hvt
No property ad found for device sky130_fd_pr__special_pfet_01v8_hvt
No property ps found for device sky130_fd_pr__special_pfet_01v8_hvt
No property pd found for device sky130_fd_pr__special_pfet_01v8_hvt
No property mult found for device sky130_fd_pr__special_pfet_01v8_hvt
No property sa found for device sky130_fd_pr__special_pfet_01v8_hvt
No property sb found for device sky130_fd_pr__special_pfet_01v8_hvt
No property sd found for device sky130_fd_pr__special_pfet_01v8_hvt
No property nf found for device sky130_fd_pr__special_pfet_01v8_hvt
No property nrd found for device sky130_fd_pr__special_pfet_01v8_hvt
No property nrs found for device sky130_fd_pr__special_pfet_01v8_hvt
No property area found for device sky130_fd_pr__special_pfet_01v8_hvt
No property perim found for device sky130_fd_pr__special_pfet_01v8_hvt
No property topography found for device sky130_fd_pr__special_pfet_01v8_hvt
No property value found for device sky130_fd_pr__diode_pw2nd_05v5
No property mult found for device sky130_fd_pr__diode_pw2nd_05v5
Comparison output logged to file /home/marwan/caravel_user_project/openlane/user_project_wrapper/runs/25_11_11_05_00/61-netgen-lvs/reports/lvs.netgen.rpt
Logging to file "/home/marwan/caravel_user_project/openlane/user_project_wrapper/runs/25_11_11_05_00/61-netgen-lvs/reports/lvs.netgen.rpt" enabled
Contents of circuit 1: Circuit: 'user_proj_example'
Circuit user_proj_example contains 0 device instances.
Circuit contains 0 nets, and 543 disconnected pins.
Contents of circuit 2: Circuit: 'user_proj_example'
Circuit user_proj_example contains 0 device instances.
Circuit contains 0 nets.
Circuit user_proj_example contains no devices.
Contents of circuit 1: Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 1 device instances.
Class: user_proj_example instances: 1
Circuit contains 543 nets, and 102 disconnected pins.
Contents of circuit 2: Circuit: 'user_project_wrapper'
Circuit user_project_wrapper contains 1 device instances.
Class: user_proj_example instances: 1
Circuit contains 543 nets, and 102 disconnected pins.
Circuit 1 contains 1 devices, Circuit 2 contains 1 devices.
Circuit 1 contains 543 nets, Circuit 2 contains 543 nets.
Final result:
Circuits match uniquely.
.
Logging to file "/home/marwan/caravel_user_project/openlane/user_project_wrapper/runs/25_11_11_05_00/61-netgen-lvs/reports/lvs.netgen.rpt" disabled
LVS Done.

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signoff/user_project_wrapper/openlane-signoff/resolved.json Normal file
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File diff suppressed because it is too large Load Diff

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signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/checks.rpt Normal file
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===========================================================================
report_checks -unconstrained
===========================================================================
======================= max_ff_n40C_1v95 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: mprj/_305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 v input external delay
2 0.029421 0.000000 0.000000 18.070000 v wb_rst_i (in)
wb_rst_i (net)
0.001994 0.000997 18.070995 v mprj/input37/A (sky130_fd_sc_hd__buf_4)
3 0.110424 0.098323 0.126377 18.197372 v mprj/input37/X (sky130_fd_sc_hd__buf_4)
mprj/net37 (net)
0.135278 0.046745 18.244118 v mprj/_153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005730 0.075903 0.116113 18.360231 ^ mprj/_153_/Y (sky130_fd_sc_hd__a21oi_4)
mprj/_039_ (net)
0.075904 0.000320 18.360552 ^ mprj/hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.005266 0.053893 0.393303 18.753855 ^ mprj/hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net324 (net)
0.053893 0.000369 18.754223 ^ mprj/hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.064470 0.481229 0.688093 19.442316 ^ mprj/hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net282 (net)
0.481325 0.006683 19.448999 ^ mprj/hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.045561 0.343535 0.616277 20.065277 ^ mprj/hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net325 (net)
0.343539 0.001823 20.067099 ^ mprj/_160_/A (sky130_fd_sc_hd__nand2_2)
2 0.016516 0.100649 0.071001 20.138100 v mprj/_160_/Y (sky130_fd_sc_hd__nand2_2)
mprj/_044_ (net)
0.100708 0.001855 20.139954 v mprj/hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.049854 0.178902 0.528459 20.668413 v mprj/hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net326 (net)
0.179036 0.004416 20.672829 v mprj/fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.138553 0.086504 0.171376 20.844206 v mprj/fanout124/X (sky130_fd_sc_hd__buf_6)
mprj/net124 (net)
0.086895 0.005862 20.850067 v mprj/_161_/A (sky130_fd_sc_hd__inv_2)
2 0.007811 0.040688 0.060034 20.910101 ^ mprj/_161_/Y (sky130_fd_sc_hd__inv_2)
mprj/_000_ (net)
0.040691 0.000369 20.910471 ^ mprj/_233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002588 0.036818 0.083903 20.994373 ^ mprj/_233_/X (sky130_fd_sc_hd__a32o_1)
mprj/_009_ (net)
0.036818 0.000108 20.994482 ^ mprj/hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002569 0.035881 0.370500 21.364981 ^ mprj/hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net431 (net)
0.035881 0.000187 21.365168 ^ mprj/hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.003126 0.039863 0.373847 21.739016 ^ mprj/hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net315 (net)
0.039863 0.000234 21.739250 ^ mprj/hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002185 0.033721 0.368708 22.107958 ^ mprj/hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net432 (net)
0.033721 0.000158 22.108114 ^ mprj/_305_/D (sky130_fd_sc_hd__dfxtp_4)
22.108114 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.052564 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.622209 0.006105 29.656105 ^ mprj/wire3/A (sky130_fd_sc_hd__buf_4)
3 0.049820 0.112676 0.158003 29.814108 ^ mprj/wire3/X (sky130_fd_sc_hd__buf_4)
mprj/net274 (net)
0.114234 0.010509 29.824617 ^ mprj/wire2/A (sky130_fd_sc_hd__buf_6)
3 0.112546 0.170017 0.169738 29.994354 ^ mprj/wire2/X (sky130_fd_sc_hd__buf_6)
mprj/net273 (net)
0.171908 0.014463 30.008818 ^ mprj/_155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.055033 0.362209 0.330900 30.339718 ^ mprj/_155_/X (sky130_fd_sc_hd__mux2_1)
mprj/clk (net)
0.362317 0.005212 30.344929 ^ mprj/wire1/A (sky130_fd_sc_hd__buf_4)
3 0.051820 0.114516 0.160306 30.505236 ^ mprj/wire1/X (sky130_fd_sc_hd__buf_4)
mprj/net272 (net)
0.116068 0.010619 30.515854 ^ mprj/clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.097281 0.088029 0.147494 30.663349 ^ mprj/clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_0_clk (net)
0.089284 0.008317 30.671665 ^ mprj/clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.068737 0.066371 0.123642 30.795307 ^ mprj/clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_2_2__leaf_clk (net)
0.071567 0.014406 30.809713 ^ mprj/_305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 30.559711 clock uncertainty
0.000000 30.559711 clock reconvergence pessimism
-0.030632 30.529081 library setup time
30.529081 data required time
---------------------------------------------------------------------------------------------
30.529081 data required time
-22.108114 data arrival time
---------------------------------------------------------------------------------------------
8.420965 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
mprj/fanout124/X 10 33 -23 (VIOLATED)
mprj/fanout125/X 10 33 -23 (VIOLATED)
mprj/_159_/Y 10 29 -19 (VIOLATED)
mprj/_156_/X 10 27 -17 (VIOLATED)
mprj/_195_/X 10 23 -13 (VIOLATED)
mprj/_182_/X 10 21 -11 (VIOLATED)
mprj/clkbuf_2_2__f_clk/X 10 21 -11 (VIOLATED)
mprj/_176_/Y 10 19 -9 (VIOLATED)
mprj/_297_/Q 10 19 -9 (VIOLATED)
mprj/clkbuf_2_1__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_3__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_0__f_clk/X 10 17 -7 (VIOLATED)
mprj/hold140/X 10 17 -7 (VIOLATED)
mprj/wire4/X 10 17 -7 (VIOLATED)
mprj/_157_/Y 10 15 -5 (VIOLATED)
mprj/_298_/Q 10 15 -5 (VIOLATED)
mprj/_301_/Q 10 15 -5 (VIOLATED)
mprj/_305_/Q 10 15 -5 (VIOLATED)
mprj/hold8/X 10 15 -5 (VIOLATED)
mprj/_228_/X 10 13 -3 (VIOLATED)
mprj/_299_/Q 10 13 -3 (VIOLATED)
mprj/_302_/Q 10 13 -3 (VIOLATED)
mprj/_303_/Q 10 13 -3 (VIOLATED)
mprj/_309_/Q 10 13 -3 (VIOLATED)
mprj/_311_/Q 10 13 -3 (VIOLATED)
mprj/_158_/Y 10 11 (VIOLATED)
mprj/_175_/X 10 11 (VIOLATED)
mprj/_300_/Q 10 11 (VIOLATED)
mprj/_308_/Q 10 11 (VIOLATED)
mprj/_310_/Q 10 11 (VIOLATED)
mprj/_312_/Q 10 11 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 186 unannotated drivers.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[8]
io_in[9]
user_clock2
mprj/clkload0/X
mprj/clkload1/X
mprj/clkload2/X
mprj/user_proj_example_141/HI
mprj/user_proj_example_142/HI
mprj/user_proj_example_143/HI
mprj/user_proj_example_144/HI
mprj/user_proj_example_145/HI
mprj/user_proj_example_146/HI
mprj/user_proj_example_147/HI
mprj/user_proj_example_148/HI
mprj/user_proj_example_149/HI
mprj/user_proj_example_150/HI
mprj/user_proj_example_151/HI
mprj/user_proj_example_152/HI
mprj/user_proj_example_153/HI
mprj/user_proj_example_154/HI
mprj/user_proj_example_155/HI
mprj/user_proj_example_156/HI
mprj/user_proj_example_157/HI
mprj/user_proj_example_158/HI
mprj/user_proj_example_159/HI
mprj/user_proj_example_160/HI
mprj/user_proj_example_161/HI
mprj/user_proj_example_162/HI
mprj/user_proj_example_163/HI
mprj/user_proj_example_164/HI
mprj/user_proj_example_165/HI
mprj/user_proj_example_166/HI
mprj/user_proj_example_167/HI
mprj/user_proj_example_168/HI
mprj/user_proj_example_169/HI
mprj/user_proj_example_170/HI
mprj/user_proj_example_171/HI
mprj/user_proj_example_172/HI
mprj/user_proj_example_173/HI
mprj/user_proj_example_174/HI
mprj/user_proj_example_175/HI
mprj/user_proj_example_176/HI
mprj/user_proj_example_177/HI
mprj/user_proj_example_178/HI
mprj/user_proj_example_179/HI
mprj/user_proj_example_180/HI
mprj/user_proj_example_181/HI
mprj/user_proj_example_182/HI
mprj/user_proj_example_183/HI
mprj/user_proj_example_184/HI
mprj/user_proj_example_185/HI
mprj/user_proj_example_186/HI
mprj/user_proj_example_187/HI
mprj/user_proj_example_188/HI
mprj/user_proj_example_189/HI
mprj/user_proj_example_190/HI
mprj/user_proj_example_191/HI
mprj/user_proj_example_192/HI
mprj/user_proj_example_193/HI
mprj/user_proj_example_194/HI
mprj/user_proj_example_195/HI
mprj/user_proj_example_196/HI
mprj/user_proj_example_197/HI
mprj/user_proj_example_198/HI
mprj/user_proj_example_199/HI
mprj/user_proj_example_200/HI
mprj/user_proj_example_201/HI
mprj/user_proj_example_202/HI
mprj/user_proj_example_203/HI
mprj/user_proj_example_204/HI
mprj/user_proj_example_205/HI
mprj/user_proj_example_206/HI
mprj/user_proj_example_207/HI
mprj/user_proj_example_208/HI
mprj/user_proj_example_209/HI
mprj/user_proj_example_210/HI
mprj/user_proj_example_211/HI
mprj/user_proj_example_212/HI
mprj/user_proj_example_213/HI
mprj/user_proj_example_214/HI
mprj/user_proj_example_215/HI
mprj/user_proj_example_216/HI
mprj/user_proj_example_217/HI
mprj/user_proj_example_218/HI
mprj/user_proj_example_219/HI
mprj/user_proj_example_220/HI
mprj/user_proj_example_221/HI
mprj/user_proj_example_222/HI
mprj/user_proj_example_223/HI
mprj/user_proj_example_224/HI
mprj/user_proj_example_225/HI
mprj/user_proj_example_226/HI
mprj/user_proj_example_227/HI
mprj/user_proj_example_228/HI
mprj/user_proj_example_229/HI
mprj/user_proj_example_230/HI
mprj/user_proj_example_231/HI
mprj/user_proj_example_232/HI
mprj/user_proj_example_233/HI
mprj/user_proj_example_234/HI
mprj/user_proj_example_235/HI
mprj/user_proj_example_236/HI
mprj/user_proj_example_237/HI
mprj/user_proj_example_238/HI
mprj/user_proj_example_239/HI
mprj/user_proj_example_240/HI
mprj/user_proj_example_241/HI
mprj/user_proj_example_242/HI
mprj/user_proj_example_243/HI
mprj/user_proj_example_244/HI
mprj/user_proj_example_245/HI
mprj/user_proj_example_246/HI
mprj/user_proj_example_247/HI
mprj/user_proj_example_248/HI
mprj/user_proj_example_249/HI
mprj/user_proj_example_250/HI
mprj/user_proj_example_251/HI
mprj/user_proj_example_252/HI
mprj/user_proj_example_253/HI
mprj/user_proj_example_254/HI
mprj/user_proj_example_255/HI
mprj/user_proj_example_256/HI
mprj/user_proj_example_257/HI
mprj/user_proj_example_258/HI
mprj/user_proj_example_259/HI
mprj/user_proj_example_260/HI
mprj/user_proj_example_261/HI
mprj/user_proj_example_262/HI
mprj/user_proj_example_263/HI
mprj/user_proj_example_264/HI
mprj/user_proj_example_265/HI
mprj/user_proj_example_266/HI
mprj/user_proj_example_267/HI
mprj/user_proj_example_268/HI
mprj/user_proj_example_269/HI
mprj/user_proj_example_270/HI
mprj/user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 31
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 68 input ports missing set_input_delay.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[1]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[2]
io_in[30]
io_in[31]
io_in[32]
io_in[33]
io_in[34]
io_in[35]
io_in[36]
io_in[37]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
user_clock2
Warning: There are 236 unconstrained endpoints.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[16]
io_oeb[17]
io_oeb[18]
io_oeb[19]
io_oeb[1]
io_oeb[20]
io_oeb[21]
io_oeb[22]
io_oeb[23]
io_oeb[24]
io_oeb[25]
io_oeb[26]
io_oeb[27]
io_oeb[28]
io_oeb[29]
io_oeb[2]
io_oeb[30]
io_oeb[31]
io_oeb[32]
io_oeb[33]
io_oeb[34]
io_oeb[35]
io_oeb[36]
io_oeb[37]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[16]
io_out[17]
io_out[18]
io_out[19]
io_out[1]
io_out[20]
io_out[21]
io_out[22]
io_out[23]
io_out[24]
io_out[25]
io_out[26]
io_out[27]
io_out[28]
io_out[29]
io_out[2]
io_out[30]
io_out[31]
io_out[32]
io_out[33]
io_out[34]
io_out[35]
io_out[36]
io_out[37]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
user_irq[0]
user_irq[1]
user_irq[2]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

51
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/clock.rpt Normal file
View File

@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
5.794850 network latency mprj/_328_/CLK
8.803080 network latency mprj/_305_/CLK
---------------
10.444851 14.373079 latency
3.928229 skew
rise -> fall
min max
4.650000 5.570000 source latency
5.886833 network latency mprj/_328_/CLK
8.789470 network latency mprj/_305_/CLK
---------------
10.536833 14.359470 latency
3.822637 skew
fall -> fall
min max
4.650000 5.570000 source latency
5.928831 network latency mprj/_328_/CLK
6.864648 network latency mprj/_305_/CLK
---------------
10.578831 12.434648 latency
1.855817 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 3.67 fmax = 272.16

4396
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/max.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

4278
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/min.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

18
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/power.rpt Normal file
View File

@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 4.245963e-05 4.360105e-05 7.394261e-10 8.606142e-05 13.4%
Combinational 1.187414e-04 3.385694e-04 1.315145e-08 4.573240e-04 71.3%
Clock 3.455815e-05 6.339366e-05 5.304953e-09 9.795711e-05 15.3%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.957592e-04 4.455642e-04 1.919599e-08 6.413427e-04 100.0%
30.5% 69.5% 0.0%

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/skew.max.rpt Normal file
View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
Clock clk
8.802965 source latency mprj/_296_/CLK ^
-5.794850 target latency mprj/_328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.258114 setup skew

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/skew.min.rpt Normal file
View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= max_ff_n40C_1v95 Corner ===================================
Clock clk
5.797908 source latency mprj/_306_/CLK ^
-6.728714 target latency mprj/_312_/CLK ^
-0.250000 clock uncertainty
-0.920002 CRPR
--------------
-2.100808 hold skew

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/tns.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
max_ff_n40C_1v95: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/tns.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
max_ff_n40C_1v95: 0.0

0
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/unpropagated.rpt Normal file
View File

4
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/violator_list.rpt Normal file
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@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/wns.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
max_ff_n40C_1v95: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/wns.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
max_ff_n40C_1v95: 0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/ws.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
max_ff_n40C_1v95: 8.420965496598887

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ff_n40C_1v95/ws.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
max_ff_n40C_1v95: 0.243695293065025

669
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/checks.rpt Normal file
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@@ -0,0 +1,669 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= max_ss_100C_1v60 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: mprj/_305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 ^ input external delay
2 0.029866 0.000000 0.000000 18.070000 ^ wb_rst_i (in)
wb_rst_i (net)
0.002043 0.001021 18.071020 ^ mprj/input37/A (sky130_fd_sc_hd__buf_4)
3 0.111563 0.490968 0.453637 18.524658 ^ mprj/input37/X (sky130_fd_sc_hd__buf_4)
mprj/net37 (net)
0.499272 0.051172 18.575829 ^ mprj/_153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005400 0.118388 0.224224 18.800055 v mprj/_153_/Y (sky130_fd_sc_hd__a21oi_4)
mprj/_039_ (net)
0.118388 0.000288 18.800341 v mprj/hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004936 0.128301 1.179540 19.979881 v mprj/hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net324 (net)
0.128301 0.000338 19.980219 v mprj/hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.063834 0.608758 1.639434 21.619652 v mprj/hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net282 (net)
0.608824 0.006569 21.626221 v mprj/hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.045452 0.455615 1.756908 23.383129 v mprj/hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net325 (net)
0.455615 0.001808 23.384937 v mprj/_160_/A (sky130_fd_sc_hd__nand2_2)
2 0.016709 0.203175 0.329708 23.714645 ^ mprj/_160_/Y (sky130_fd_sc_hd__nand2_2)
mprj/_044_ (net)
0.203190 0.001879 23.716524 ^ mprj/hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.050872 0.768606 1.615794 25.332317 ^ mprj/hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net326 (net)
0.768623 0.004578 25.336897 ^ mprj/fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.141612 0.447056 0.662691 25.999588 ^ mprj/fanout124/X (sky130_fd_sc_hd__buf_6)
mprj/net124 (net)
0.447163 0.006048 26.005636 ^ mprj/_161_/A (sky130_fd_sc_hd__inv_2)
2 0.007357 0.099004 0.181235 26.186871 v mprj/_161_/Y (sky130_fd_sc_hd__inv_2)
mprj/_000_ (net)
0.099004 0.000346 26.187216 v mprj/_233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002258 0.066735 0.438190 26.625406 v mprj/_233_/X (sky130_fd_sc_hd__a32o_1)
mprj/_009_ (net)
0.066735 0.000092 26.625500 v mprj/hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002239 0.101244 1.112467 27.737967 v mprj/hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net431 (net)
0.101244 0.000160 27.738125 v mprj/hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002796 0.105541 1.137940 28.876064 v mprj/hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net315 (net)
0.105541 0.000208 28.876272 v mprj/hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.001921 0.098113 1.125233 30.001507 v mprj/hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net432 (net)
0.098113 0.000139 30.001644 v mprj/_305_/D (sky130_fd_sc_hd__dfxtp_4)
30.001644 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.052715 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.622287 0.006144 29.656143 ^ mprj/wire3/A (sky130_fd_sc_hd__buf_4)
3 0.050133 0.234641 0.555509 30.211653 ^ mprj/wire3/X (sky130_fd_sc_hd__buf_4)
mprj/net274 (net)
0.235516 0.010623 30.222275 ^ mprj/wire2/A (sky130_fd_sc_hd__buf_6)
3 0.112773 0.356296 0.457199 30.679474 ^ mprj/wire2/X (sky130_fd_sc_hd__buf_6)
mprj/net273 (net)
0.357179 0.014580 30.694054 ^ mprj/_155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.055386 0.769394 0.863743 31.557796 ^ mprj/_155_/X (sky130_fd_sc_hd__mux2_1)
mprj/clk (net)
0.769420 0.005244 31.563042 ^ mprj/wire1/A (sky130_fd_sc_hd__buf_4)
3 0.052155 0.244788 0.600860 32.163902 ^ mprj/wire1/X (sky130_fd_sc_hd__buf_4)
mprj/net272 (net)
0.245654 0.010747 32.174648 ^ mprj/clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.098015 0.174219 0.388955 32.563602 ^ mprj/clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_0_clk (net)
0.174993 0.008434 32.572037 ^ mprj/clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.068929 0.133024 0.325134 32.897171 ^ mprj/clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_2_2__leaf_clk (net)
0.135672 0.014722 32.911892 ^ mprj/_305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 32.661892 clock uncertainty
0.000000 32.661892 clock reconvergence pessimism
-0.267000 32.394890 library setup time
32.394890 data required time
---------------------------------------------------------------------------------------------
32.394890 data required time
-30.001644 data arrival time
---------------------------------------------------------------------------------------------
2.393247 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
max slew
Pin Limit Slew Slack
------------------------------------------------------------------------
mprj/_152_/B 1.500000 1.581131 -0.081131 (VIOLATED)
mprj/ANTENNA__152__B/DIODE 1.500000 1.581118 -0.081119 (VIOLATED)
mprj/hold48/X 1.498918 1.578304 -0.079386 (VIOLATED)
mprj/ANTENNA_hold48_X/DIODE 1.500000 1.578318 -0.078318 (VIOLATED)
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
mprj/fanout124/X 10 33 -23 (VIOLATED)
mprj/fanout125/X 10 33 -23 (VIOLATED)
mprj/_159_/Y 10 29 -19 (VIOLATED)
mprj/_156_/X 10 27 -17 (VIOLATED)
mprj/_195_/X 10 23 -13 (VIOLATED)
mprj/_182_/X 10 21 -11 (VIOLATED)
mprj/clkbuf_2_2__f_clk/X 10 21 -11 (VIOLATED)
mprj/_176_/Y 10 19 -9 (VIOLATED)
mprj/_297_/Q 10 19 -9 (VIOLATED)
mprj/clkbuf_2_1__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_3__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_0__f_clk/X 10 17 -7 (VIOLATED)
mprj/hold140/X 10 17 -7 (VIOLATED)
mprj/wire4/X 10 17 -7 (VIOLATED)
mprj/_157_/Y 10 15 -5 (VIOLATED)
mprj/_298_/Q 10 15 -5 (VIOLATED)
mprj/_301_/Q 10 15 -5 (VIOLATED)
mprj/_305_/Q 10 15 -5 (VIOLATED)
mprj/hold8/X 10 15 -5 (VIOLATED)
mprj/_228_/X 10 13 -3 (VIOLATED)
mprj/_299_/Q 10 13 -3 (VIOLATED)
mprj/_302_/Q 10 13 -3 (VIOLATED)
mprj/_303_/Q 10 13 -3 (VIOLATED)
mprj/_309_/Q 10 13 -3 (VIOLATED)
mprj/_311_/Q 10 13 -3 (VIOLATED)
mprj/_158_/Y 10 11 (VIOLATED)
mprj/_175_/X 10 11 (VIOLATED)
mprj/_300_/Q 10 11 (VIOLATED)
mprj/_308_/Q 10 11 (VIOLATED)
mprj/_310_/Q 10 11 (VIOLATED)
mprj/_312_/Q 10 11 (VIOLATED)
max capacitance
Pin Limit Cap Slack
------------------------------------------------------------------------
mprj/hold48/X 0.100718 0.106189 -0.005471 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 186 unannotated drivers.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[8]
io_in[9]
user_clock2
mprj/clkload0/X
mprj/clkload1/X
mprj/clkload2/X
mprj/user_proj_example_141/HI
mprj/user_proj_example_142/HI
mprj/user_proj_example_143/HI
mprj/user_proj_example_144/HI
mprj/user_proj_example_145/HI
mprj/user_proj_example_146/HI
mprj/user_proj_example_147/HI
mprj/user_proj_example_148/HI
mprj/user_proj_example_149/HI
mprj/user_proj_example_150/HI
mprj/user_proj_example_151/HI
mprj/user_proj_example_152/HI
mprj/user_proj_example_153/HI
mprj/user_proj_example_154/HI
mprj/user_proj_example_155/HI
mprj/user_proj_example_156/HI
mprj/user_proj_example_157/HI
mprj/user_proj_example_158/HI
mprj/user_proj_example_159/HI
mprj/user_proj_example_160/HI
mprj/user_proj_example_161/HI
mprj/user_proj_example_162/HI
mprj/user_proj_example_163/HI
mprj/user_proj_example_164/HI
mprj/user_proj_example_165/HI
mprj/user_proj_example_166/HI
mprj/user_proj_example_167/HI
mprj/user_proj_example_168/HI
mprj/user_proj_example_169/HI
mprj/user_proj_example_170/HI
mprj/user_proj_example_171/HI
mprj/user_proj_example_172/HI
mprj/user_proj_example_173/HI
mprj/user_proj_example_174/HI
mprj/user_proj_example_175/HI
mprj/user_proj_example_176/HI
mprj/user_proj_example_177/HI
mprj/user_proj_example_178/HI
mprj/user_proj_example_179/HI
mprj/user_proj_example_180/HI
mprj/user_proj_example_181/HI
mprj/user_proj_example_182/HI
mprj/user_proj_example_183/HI
mprj/user_proj_example_184/HI
mprj/user_proj_example_185/HI
mprj/user_proj_example_186/HI
mprj/user_proj_example_187/HI
mprj/user_proj_example_188/HI
mprj/user_proj_example_189/HI
mprj/user_proj_example_190/HI
mprj/user_proj_example_191/HI
mprj/user_proj_example_192/HI
mprj/user_proj_example_193/HI
mprj/user_proj_example_194/HI
mprj/user_proj_example_195/HI
mprj/user_proj_example_196/HI
mprj/user_proj_example_197/HI
mprj/user_proj_example_198/HI
mprj/user_proj_example_199/HI
mprj/user_proj_example_200/HI
mprj/user_proj_example_201/HI
mprj/user_proj_example_202/HI
mprj/user_proj_example_203/HI
mprj/user_proj_example_204/HI
mprj/user_proj_example_205/HI
mprj/user_proj_example_206/HI
mprj/user_proj_example_207/HI
mprj/user_proj_example_208/HI
mprj/user_proj_example_209/HI
mprj/user_proj_example_210/HI
mprj/user_proj_example_211/HI
mprj/user_proj_example_212/HI
mprj/user_proj_example_213/HI
mprj/user_proj_example_214/HI
mprj/user_proj_example_215/HI
mprj/user_proj_example_216/HI
mprj/user_proj_example_217/HI
mprj/user_proj_example_218/HI
mprj/user_proj_example_219/HI
mprj/user_proj_example_220/HI
mprj/user_proj_example_221/HI
mprj/user_proj_example_222/HI
mprj/user_proj_example_223/HI
mprj/user_proj_example_224/HI
mprj/user_proj_example_225/HI
mprj/user_proj_example_226/HI
mprj/user_proj_example_227/HI
mprj/user_proj_example_228/HI
mprj/user_proj_example_229/HI
mprj/user_proj_example_230/HI
mprj/user_proj_example_231/HI
mprj/user_proj_example_232/HI
mprj/user_proj_example_233/HI
mprj/user_proj_example_234/HI
mprj/user_proj_example_235/HI
mprj/user_proj_example_236/HI
mprj/user_proj_example_237/HI
mprj/user_proj_example_238/HI
mprj/user_proj_example_239/HI
mprj/user_proj_example_240/HI
mprj/user_proj_example_241/HI
mprj/user_proj_example_242/HI
mprj/user_proj_example_243/HI
mprj/user_proj_example_244/HI
mprj/user_proj_example_245/HI
mprj/user_proj_example_246/HI
mprj/user_proj_example_247/HI
mprj/user_proj_example_248/HI
mprj/user_proj_example_249/HI
mprj/user_proj_example_250/HI
mprj/user_proj_example_251/HI
mprj/user_proj_example_252/HI
mprj/user_proj_example_253/HI
mprj/user_proj_example_254/HI
mprj/user_proj_example_255/HI
mprj/user_proj_example_256/HI
mprj/user_proj_example_257/HI
mprj/user_proj_example_258/HI
mprj/user_proj_example_259/HI
mprj/user_proj_example_260/HI
mprj/user_proj_example_261/HI
mprj/user_proj_example_262/HI
mprj/user_proj_example_263/HI
mprj/user_proj_example_264/HI
mprj/user_proj_example_265/HI
mprj/user_proj_example_266/HI
mprj/user_proj_example_267/HI
mprj/user_proj_example_268/HI
mprj/user_proj_example_269/HI
mprj/user_proj_example_270/HI
mprj/user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 4
max fanout violation count 31
max cap violation count 1
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 68 input ports missing set_input_delay.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[1]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[2]
io_in[30]
io_in[31]
io_in[32]
io_in[33]
io_in[34]
io_in[35]
io_in[36]
io_in[37]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
user_clock2
Warning: There are 236 unconstrained endpoints.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[16]
io_oeb[17]
io_oeb[18]
io_oeb[19]
io_oeb[1]
io_oeb[20]
io_oeb[21]
io_oeb[22]
io_oeb[23]
io_oeb[24]
io_oeb[25]
io_oeb[26]
io_oeb[27]
io_oeb[28]
io_oeb[29]
io_oeb[2]
io_oeb[30]
io_oeb[31]
io_oeb[32]
io_oeb[33]
io_oeb[34]
io_oeb[35]
io_oeb[36]
io_oeb[37]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[16]
io_out[17]
io_out[18]
io_out[19]
io_out[1]
io_out[20]
io_out[21]
io_out[22]
io_out[23]
io_out[24]
io_out[25]
io_out[26]
io_out[27]
io_out[28]
io_out[29]
io_out[2]
io_out[30]
io_out[31]
io_out[32]
io_out[33]
io_out[34]
io_out[35]
io_out[36]
io_out[37]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
user_irq[0]
user_irq[1]
user_irq[2]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

51
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/clock.rpt Normal file
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@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
7.704398 network latency mprj/_328_/CLK
10.646440 network latency mprj/_305_/CLK
---------------
12.354399 16.216440 latency
3.862041 skew
rise -> fall
min max
4.650000 5.570000 source latency
7.735256 network latency mprj/_328_/CLK
10.841234 network latency mprj/_305_/CLK
---------------
12.385256 16.411234 latency
4.025978 skew
fall -> fall
min max
4.650000 5.570000 source latency
8.006374 network latency mprj/_328_/CLK
8.944438 network latency mprj/_305_/CLK
---------------
12.656374 14.514438 latency
1.858064 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 10.83 fmax = 92.37

4396
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/max.rpt Normal file
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File diff suppressed because it is too large Load Diff

4239
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/min.rpt Normal file
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File diff suppressed because it is too large Load Diff

18
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/power.rpt Normal file
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@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 2.903494e-05 2.930423e-05 5.104404e-07 5.884961e-05 13.4%
Combinational 8.203297e-05 2.277471e-04 3.839341e-06 3.136194e-04 71.3%
Clock 2.463859e-05 4.285167e-05 1.530292e-07 6.764329e-05 15.4%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.357065e-04 2.999030e-04 4.502832e-06 4.401123e-04 100.0%
30.8% 68.1% 1.0%

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/skew.max.rpt Normal file
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@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
Clock clk
10.646317 source latency mprj/_296_/CLK ^
-7.891549 target latency mprj/_328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.004769 setup skew

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/skew.min.rpt Normal file
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@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= max_ss_100C_1v60 Corner ===================================
Clock clk
7.898979 source latency mprj/_306_/CLK ^
-8.830502 target latency mprj/_312_/CLK ^
-0.250000 clock uncertainty
-0.920459 CRPR
--------------
-2.101983 hold skew

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/tns.max.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
max_ss_100C_1v60: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/tns.min.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
max_ss_100C_1v60: 0.0

0
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/unpropagated.rpt Normal file
View File

4
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/violator_list.rpt Normal file
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@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/wns.max.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
max_ss_100C_1v60: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/wns.min.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
max_ss_100C_1v60: 0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/ws.max.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
max_ss_100C_1v60: 2.393246557559126

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_ss_100C_1v60/ws.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
max_ss_100C_1v60: 0.9999921174163022

654
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/checks.rpt Normal file
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@@ -0,0 +1,654 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= max_tt_025C_1v80 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: mprj/_305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 ^ input external delay
2 0.029772 0.000000 0.000000 18.070000 ^ wb_rst_i (in)
wb_rst_i (net)
0.002035 0.001018 18.071016 ^ mprj/input37/A (sky130_fd_sc_hd__buf_4)
3 0.111363 0.308380 0.256980 18.327997 ^ mprj/input37/X (sky130_fd_sc_hd__buf_4)
mprj/net37 (net)
0.321741 0.050331 18.378328 ^ mprj/_153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005451 0.072267 0.086493 18.464821 v mprj/_153_/Y (sky130_fd_sc_hd__a21oi_4)
mprj/_039_ (net)
0.072268 0.000293 18.465115 v mprj/hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004987 0.063794 0.575684 19.040798 v mprj/hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net324 (net)
0.063794 0.000343 19.041142 v mprj/hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.063174 0.309341 0.806931 19.848072 v mprj/hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net282 (net)
0.309500 0.006496 19.854568 v mprj/hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.044986 0.236934 0.850402 20.704971 v mprj/hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net325 (net)
0.236944 0.001791 20.706760 v mprj/_160_/A (sky130_fd_sc_hd__nand2_2)
2 0.016700 0.116986 0.178462 20.885223 ^ mprj/_160_/Y (sky130_fd_sc_hd__nand2_2)
mprj/_044_ (net)
0.117089 0.001881 20.887104 ^ mprj/hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.050752 0.497264 0.882233 21.769337 ^ mprj/hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net326 (net)
0.497300 0.004560 21.773897 ^ mprj/fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.142286 0.284702 0.322210 22.096107 ^ mprj/fanout124/X (sky130_fd_sc_hd__buf_6)
mprj/net124 (net)
0.284864 0.006070 22.102177 ^ mprj/_161_/A (sky130_fd_sc_hd__inv_2)
2 0.007416 0.061816 0.070321 22.172497 v mprj/_161_/Y (sky130_fd_sc_hd__inv_2)
mprj/_000_ (net)
0.061819 0.000346 22.172844 v mprj/_233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002309 0.038889 0.241434 22.414278 v mprj/_233_/X (sky130_fd_sc_hd__a32o_1)
mprj/_009_ (net)
0.038889 0.000094 22.414371 v mprj/hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002290 0.050240 0.541128 22.955500 v mprj/hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net431 (net)
0.050240 0.000165 22.955666 v mprj/hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002847 0.053229 0.550589 23.506254 v mprj/hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net315 (net)
0.053229 0.000211 23.506466 v mprj/hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002020 0.049067 0.544267 24.050732 v mprj/hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net432 (net)
0.049067 0.000146 24.050877 v mprj/_305_/D (sky130_fd_sc_hd__dfxtp_4)
24.050877 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.052621 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.622238 0.006120 29.656118 ^ mprj/wire3/A (sky130_fd_sc_hd__buf_4)
3 0.049956 0.148858 0.305967 29.962086 ^ mprj/wire3/X (sky130_fd_sc_hd__buf_4)
mprj/net274 (net)
0.150012 0.010555 29.972641 ^ mprj/wire2/A (sky130_fd_sc_hd__buf_6)
3 0.112631 0.225562 0.253365 30.226006 ^ mprj/wire2/X (sky130_fd_sc_hd__buf_6)
mprj/net273 (net)
0.226972 0.014516 30.240522 ^ mprj/_155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.055185 0.482949 0.488491 30.729013 ^ mprj/_155_/X (sky130_fd_sc_hd__mux2_1)
mprj/clk (net)
0.483029 0.005222 30.734236 ^ mprj/wire1/A (sky130_fd_sc_hd__buf_4)
3 0.051941 0.152289 0.287500 31.021736 ^ mprj/wire1/X (sky130_fd_sc_hd__buf_4)
mprj/net272 (net)
0.153434 0.010665 31.032400 ^ mprj/clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.097480 0.114495 0.218130 31.250530 ^ mprj/clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_0_clk (net)
0.115440 0.008352 31.258883 ^ mprj/clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.068926 0.087363 0.183725 31.442608 ^ mprj/clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_2_2__leaf_clk (net)
0.091346 0.014580 31.457188 ^ mprj/_305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 31.207188 clock uncertainty
0.000000 31.207188 clock reconvergence pessimism
-0.103199 31.103989 library setup time
31.103989 data required time
---------------------------------------------------------------------------------------------
31.103989 data required time
-24.050877 data arrival time
---------------------------------------------------------------------------------------------
7.053110 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
mprj/fanout124/X 10 33 -23 (VIOLATED)
mprj/fanout125/X 10 33 -23 (VIOLATED)
mprj/_159_/Y 10 29 -19 (VIOLATED)
mprj/_156_/X 10 27 -17 (VIOLATED)
mprj/_195_/X 10 23 -13 (VIOLATED)
mprj/_182_/X 10 21 -11 (VIOLATED)
mprj/clkbuf_2_2__f_clk/X 10 21 -11 (VIOLATED)
mprj/_176_/Y 10 19 -9 (VIOLATED)
mprj/_297_/Q 10 19 -9 (VIOLATED)
mprj/clkbuf_2_1__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_3__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_0__f_clk/X 10 17 -7 (VIOLATED)
mprj/hold140/X 10 17 -7 (VIOLATED)
mprj/wire4/X 10 17 -7 (VIOLATED)
mprj/_157_/Y 10 15 -5 (VIOLATED)
mprj/_298_/Q 10 15 -5 (VIOLATED)
mprj/_301_/Q 10 15 -5 (VIOLATED)
mprj/_305_/Q 10 15 -5 (VIOLATED)
mprj/hold8/X 10 15 -5 (VIOLATED)
mprj/_228_/X 10 13 -3 (VIOLATED)
mprj/_299_/Q 10 13 -3 (VIOLATED)
mprj/_302_/Q 10 13 -3 (VIOLATED)
mprj/_303_/Q 10 13 -3 (VIOLATED)
mprj/_309_/Q 10 13 -3 (VIOLATED)
mprj/_311_/Q 10 13 -3 (VIOLATED)
mprj/_158_/Y 10 11 (VIOLATED)
mprj/_175_/X 10 11 (VIOLATED)
mprj/_300_/Q 10 11 (VIOLATED)
mprj/_308_/Q 10 11 (VIOLATED)
mprj/_310_/Q 10 11 (VIOLATED)
mprj/_312_/Q 10 11 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 186 unannotated drivers.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[8]
io_in[9]
user_clock2
mprj/clkload0/X
mprj/clkload1/X
mprj/clkload2/X
mprj/user_proj_example_141/HI
mprj/user_proj_example_142/HI
mprj/user_proj_example_143/HI
mprj/user_proj_example_144/HI
mprj/user_proj_example_145/HI
mprj/user_proj_example_146/HI
mprj/user_proj_example_147/HI
mprj/user_proj_example_148/HI
mprj/user_proj_example_149/HI
mprj/user_proj_example_150/HI
mprj/user_proj_example_151/HI
mprj/user_proj_example_152/HI
mprj/user_proj_example_153/HI
mprj/user_proj_example_154/HI
mprj/user_proj_example_155/HI
mprj/user_proj_example_156/HI
mprj/user_proj_example_157/HI
mprj/user_proj_example_158/HI
mprj/user_proj_example_159/HI
mprj/user_proj_example_160/HI
mprj/user_proj_example_161/HI
mprj/user_proj_example_162/HI
mprj/user_proj_example_163/HI
mprj/user_proj_example_164/HI
mprj/user_proj_example_165/HI
mprj/user_proj_example_166/HI
mprj/user_proj_example_167/HI
mprj/user_proj_example_168/HI
mprj/user_proj_example_169/HI
mprj/user_proj_example_170/HI
mprj/user_proj_example_171/HI
mprj/user_proj_example_172/HI
mprj/user_proj_example_173/HI
mprj/user_proj_example_174/HI
mprj/user_proj_example_175/HI
mprj/user_proj_example_176/HI
mprj/user_proj_example_177/HI
mprj/user_proj_example_178/HI
mprj/user_proj_example_179/HI
mprj/user_proj_example_180/HI
mprj/user_proj_example_181/HI
mprj/user_proj_example_182/HI
mprj/user_proj_example_183/HI
mprj/user_proj_example_184/HI
mprj/user_proj_example_185/HI
mprj/user_proj_example_186/HI
mprj/user_proj_example_187/HI
mprj/user_proj_example_188/HI
mprj/user_proj_example_189/HI
mprj/user_proj_example_190/HI
mprj/user_proj_example_191/HI
mprj/user_proj_example_192/HI
mprj/user_proj_example_193/HI
mprj/user_proj_example_194/HI
mprj/user_proj_example_195/HI
mprj/user_proj_example_196/HI
mprj/user_proj_example_197/HI
mprj/user_proj_example_198/HI
mprj/user_proj_example_199/HI
mprj/user_proj_example_200/HI
mprj/user_proj_example_201/HI
mprj/user_proj_example_202/HI
mprj/user_proj_example_203/HI
mprj/user_proj_example_204/HI
mprj/user_proj_example_205/HI
mprj/user_proj_example_206/HI
mprj/user_proj_example_207/HI
mprj/user_proj_example_208/HI
mprj/user_proj_example_209/HI
mprj/user_proj_example_210/HI
mprj/user_proj_example_211/HI
mprj/user_proj_example_212/HI
mprj/user_proj_example_213/HI
mprj/user_proj_example_214/HI
mprj/user_proj_example_215/HI
mprj/user_proj_example_216/HI
mprj/user_proj_example_217/HI
mprj/user_proj_example_218/HI
mprj/user_proj_example_219/HI
mprj/user_proj_example_220/HI
mprj/user_proj_example_221/HI
mprj/user_proj_example_222/HI
mprj/user_proj_example_223/HI
mprj/user_proj_example_224/HI
mprj/user_proj_example_225/HI
mprj/user_proj_example_226/HI
mprj/user_proj_example_227/HI
mprj/user_proj_example_228/HI
mprj/user_proj_example_229/HI
mprj/user_proj_example_230/HI
mprj/user_proj_example_231/HI
mprj/user_proj_example_232/HI
mprj/user_proj_example_233/HI
mprj/user_proj_example_234/HI
mprj/user_proj_example_235/HI
mprj/user_proj_example_236/HI
mprj/user_proj_example_237/HI
mprj/user_proj_example_238/HI
mprj/user_proj_example_239/HI
mprj/user_proj_example_240/HI
mprj/user_proj_example_241/HI
mprj/user_proj_example_242/HI
mprj/user_proj_example_243/HI
mprj/user_proj_example_244/HI
mprj/user_proj_example_245/HI
mprj/user_proj_example_246/HI
mprj/user_proj_example_247/HI
mprj/user_proj_example_248/HI
mprj/user_proj_example_249/HI
mprj/user_proj_example_250/HI
mprj/user_proj_example_251/HI
mprj/user_proj_example_252/HI
mprj/user_proj_example_253/HI
mprj/user_proj_example_254/HI
mprj/user_proj_example_255/HI
mprj/user_proj_example_256/HI
mprj/user_proj_example_257/HI
mprj/user_proj_example_258/HI
mprj/user_proj_example_259/HI
mprj/user_proj_example_260/HI
mprj/user_proj_example_261/HI
mprj/user_proj_example_262/HI
mprj/user_proj_example_263/HI
mprj/user_proj_example_264/HI
mprj/user_proj_example_265/HI
mprj/user_proj_example_266/HI
mprj/user_proj_example_267/HI
mprj/user_proj_example_268/HI
mprj/user_proj_example_269/HI
mprj/user_proj_example_270/HI
mprj/user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 31
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 68 input ports missing set_input_delay.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[1]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[2]
io_in[30]
io_in[31]
io_in[32]
io_in[33]
io_in[34]
io_in[35]
io_in[36]
io_in[37]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
user_clock2
Warning: There are 236 unconstrained endpoints.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[16]
io_oeb[17]
io_oeb[18]
io_oeb[19]
io_oeb[1]
io_oeb[20]
io_oeb[21]
io_oeb[22]
io_oeb[23]
io_oeb[24]
io_oeb[25]
io_oeb[26]
io_oeb[27]
io_oeb[28]
io_oeb[29]
io_oeb[2]
io_oeb[30]
io_oeb[31]
io_oeb[32]
io_oeb[33]
io_oeb[34]
io_oeb[35]
io_oeb[36]
io_oeb[37]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[16]
io_out[17]
io_out[18]
io_out[19]
io_out[1]
io_out[20]
io_out[21]
io_out[22]
io_out[23]
io_out[24]
io_out[25]
io_out[26]
io_out[27]
io_out[28]
io_out[29]
io_out[2]
io_out[30]
io_out[31]
io_out[32]
io_out[33]
io_out[34]
io_out[35]
io_out[36]
io_out[37]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
user_irq[0]
user_irq[1]
user_irq[2]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

51
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/clock.rpt Normal file
View File

@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
6.423130 network latency mprj/_328_/CLK
9.349173 network latency mprj/_305_/CLK
---------------
11.073131 14.919172 latency
3.846042 skew
rise -> fall
min max
4.650000 5.570000 source latency
6.394101 network latency mprj/_328_/CLK
9.341503 network latency mprj/_305_/CLK
---------------
11.044101 14.911504 latency
3.867403 skew
fall -> fall
min max
4.650000 5.570000 source latency
6.522374 network latency mprj/_328_/CLK
7.456866 network latency mprj/_305_/CLK
---------------
11.172374 13.026865 latency
1.854492 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 5.49 fmax = 182.10

4396
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/max.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

4251
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/min.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

18
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/power.rpt Normal file
View File

@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 3.688020e-05 3.715193e-05 2.838373e-10 7.403241e-05 13.5%
Combinational 1.020918e-04 2.883485e-04 3.073229e-09 3.904434e-04 71.1%
Clock 3.016737e-05 5.416015e-05 4.242312e-09 8.433177e-05 15.4%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.691394e-04 3.796606e-04 7.599371e-09 5.488077e-04 100.0%
30.8% 69.2% 0.0%

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/skew.max.rpt Normal file
View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
Clock clk
9.349054 source latency mprj/_296_/CLK ^
-6.440582 target latency mprj/_328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.158472 setup skew

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/skew.min.rpt Normal file
View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= max_tt_025C_1v80 Corner ===================================
Clock clk
6.444930 source latency mprj/_306_/CLK ^
-7.376017 target latency mprj/_312_/CLK ^
-0.250000 clock uncertainty
-0.920141 CRPR
--------------
-2.101228 hold skew

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/tns.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
max_tt_025C_1v80: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/tns.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
max_tt_025C_1v80: 0.0

0
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/unpropagated.rpt Normal file
View File

4
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/violator_list.rpt Normal file
View File

@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/wns.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
max_tt_025C_1v80: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/wns.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
max_tt_025C_1v80: 0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/ws.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
max_tt_025C_1v80: 7.0531102954425675

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/max_tt_025C_1v80/ws.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
max_tt_025C_1v80: 0.33149040006776803

654
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/checks.rpt Normal file
View File

@@ -0,0 +1,654 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= min_ff_n40C_1v95 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: mprj/_305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 v input external delay
2 0.025006 0.000000 0.000000 18.070000 v wb_rst_i (in)
wb_rst_i (net)
0.000847 0.000423 18.070421 v mprj/input37/A (sky130_fd_sc_hd__buf_4)
3 0.098721 0.091806 0.130424 18.200846 v mprj/input37/X (sky130_fd_sc_hd__buf_4)
mprj/net37 (net)
0.105462 0.026697 18.227543 v mprj/_153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.005116 0.072899 0.104112 18.331656 ^ mprj/_153_/Y (sky130_fd_sc_hd__a21oi_4)
mprj/_039_ (net)
0.072900 0.000099 18.331755 ^ mprj/hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004676 0.049993 0.389726 18.721479 ^ mprj/hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net324 (net)
0.049993 0.000083 18.721563 ^ mprj/hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.058232 0.435321 0.658515 19.380079 ^ mprj/hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net282 (net)
0.435322 0.001776 19.381855 ^ mprj/hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.040854 0.308938 0.593872 19.975727 ^ mprj/hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net325 (net)
0.308938 0.000522 19.976250 ^ mprj/_160_/A (sky130_fd_sc_hd__nand2_2)
2 0.014720 0.091891 0.067043 20.043291 v mprj/_160_/Y (sky130_fd_sc_hd__nand2_2)
mprj/_044_ (net)
0.091902 0.000759 20.044050 v mprj/hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.044886 0.163908 0.514147 20.558197 v mprj/hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net326 (net)
0.163917 0.001330 20.559528 v mprj/fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.128472 0.084558 0.175357 20.734884 v mprj/fanout124/X (sky130_fd_sc_hd__buf_6)
mprj/net124 (net)
0.084568 0.000806 20.735691 v mprj/_161_/A (sky130_fd_sc_hd__inv_2)
2 0.007256 0.038757 0.057851 20.793541 ^ mprj/_161_/Y (sky130_fd_sc_hd__inv_2)
mprj/_000_ (net)
0.038757 0.000048 20.793591 ^ mprj/_233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002475 0.035375 0.082816 20.876406 ^ mprj/_233_/X (sky130_fd_sc_hd__a32o_1)
mprj/_009_ (net)
0.035375 0.000014 20.876419 ^ mprj/hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002425 0.035111 0.369329 21.245749 ^ mprj/hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net431 (net)
0.035111 0.000025 21.245773 ^ mprj/hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002915 0.038074 0.372408 21.618181 ^ mprj/hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net315 (net)
0.038074 0.000034 21.618216 ^ mprj/hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002098 0.033302 0.367811 21.986027 ^ mprj/hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net432 (net)
0.033302 0.000020 21.986046 ^ mprj/_305_/D (sky130_fd_sc_hd__dfxtp_4)
21.986046 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.045901 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.616675 0.003338 29.653337 ^ mprj/wire3/A (sky130_fd_sc_hd__buf_4)
3 0.043568 0.101203 0.151800 29.805138 ^ mprj/wire3/X (sky130_fd_sc_hd__buf_4)
mprj/net274 (net)
0.101640 0.005283 29.810419 ^ mprj/wire2/A (sky130_fd_sc_hd__buf_6)
3 0.098274 0.148670 0.159492 29.969912 ^ mprj/wire2/X (sky130_fd_sc_hd__buf_6)
mprj/net273 (net)
0.149031 0.005997 29.975908 ^ mprj/_155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.049782 0.327862 0.307587 30.283495 ^ mprj/_155_/X (sky130_fd_sc_hd__mux2_1)
mprj/clk (net)
0.327878 0.001890 30.285385 ^ mprj/wire1/A (sky130_fd_sc_hd__buf_4)
3 0.046498 0.103382 0.155868 30.441254 ^ mprj/wire1/X (sky130_fd_sc_hd__buf_4)
mprj/net272 (net)
0.103828 0.005450 30.446703 ^ mprj/clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.090564 0.082419 0.143014 30.589718 ^ mprj/clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_0_clk (net)
0.082737 0.004089 30.593807 ^ mprj/clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.062058 0.061268 0.122295 30.716103 ^ mprj/clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_2_2__leaf_clk (net)
0.061823 0.004572 30.720675 ^ mprj/_305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 30.470675 clock uncertainty
0.000000 30.470675 clock reconvergence pessimism
-0.030882 30.439795 library setup time
30.439795 data required time
---------------------------------------------------------------------------------------------
30.439795 data required time
-21.986046 data arrival time
---------------------------------------------------------------------------------------------
8.453748 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
mprj/fanout124/X 10 33 -23 (VIOLATED)
mprj/fanout125/X 10 33 -23 (VIOLATED)
mprj/_159_/Y 10 29 -19 (VIOLATED)
mprj/_156_/X 10 27 -17 (VIOLATED)
mprj/_195_/X 10 23 -13 (VIOLATED)
mprj/_182_/X 10 21 -11 (VIOLATED)
mprj/clkbuf_2_2__f_clk/X 10 21 -11 (VIOLATED)
mprj/_176_/Y 10 19 -9 (VIOLATED)
mprj/_297_/Q 10 19 -9 (VIOLATED)
mprj/clkbuf_2_1__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_3__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_0__f_clk/X 10 17 -7 (VIOLATED)
mprj/hold140/X 10 17 -7 (VIOLATED)
mprj/wire4/X 10 17 -7 (VIOLATED)
mprj/_157_/Y 10 15 -5 (VIOLATED)
mprj/_298_/Q 10 15 -5 (VIOLATED)
mprj/_301_/Q 10 15 -5 (VIOLATED)
mprj/_305_/Q 10 15 -5 (VIOLATED)
mprj/hold8/X 10 15 -5 (VIOLATED)
mprj/_228_/X 10 13 -3 (VIOLATED)
mprj/_299_/Q 10 13 -3 (VIOLATED)
mprj/_302_/Q 10 13 -3 (VIOLATED)
mprj/_303_/Q 10 13 -3 (VIOLATED)
mprj/_309_/Q 10 13 -3 (VIOLATED)
mprj/_311_/Q 10 13 -3 (VIOLATED)
mprj/_158_/Y 10 11 (VIOLATED)
mprj/_175_/X 10 11 (VIOLATED)
mprj/_300_/Q 10 11 (VIOLATED)
mprj/_308_/Q 10 11 (VIOLATED)
mprj/_310_/Q 10 11 (VIOLATED)
mprj/_312_/Q 10 11 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 186 unannotated drivers.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[8]
io_in[9]
user_clock2
mprj/clkload0/X
mprj/clkload1/X
mprj/clkload2/X
mprj/user_proj_example_141/HI
mprj/user_proj_example_142/HI
mprj/user_proj_example_143/HI
mprj/user_proj_example_144/HI
mprj/user_proj_example_145/HI
mprj/user_proj_example_146/HI
mprj/user_proj_example_147/HI
mprj/user_proj_example_148/HI
mprj/user_proj_example_149/HI
mprj/user_proj_example_150/HI
mprj/user_proj_example_151/HI
mprj/user_proj_example_152/HI
mprj/user_proj_example_153/HI
mprj/user_proj_example_154/HI
mprj/user_proj_example_155/HI
mprj/user_proj_example_156/HI
mprj/user_proj_example_157/HI
mprj/user_proj_example_158/HI
mprj/user_proj_example_159/HI
mprj/user_proj_example_160/HI
mprj/user_proj_example_161/HI
mprj/user_proj_example_162/HI
mprj/user_proj_example_163/HI
mprj/user_proj_example_164/HI
mprj/user_proj_example_165/HI
mprj/user_proj_example_166/HI
mprj/user_proj_example_167/HI
mprj/user_proj_example_168/HI
mprj/user_proj_example_169/HI
mprj/user_proj_example_170/HI
mprj/user_proj_example_171/HI
mprj/user_proj_example_172/HI
mprj/user_proj_example_173/HI
mprj/user_proj_example_174/HI
mprj/user_proj_example_175/HI
mprj/user_proj_example_176/HI
mprj/user_proj_example_177/HI
mprj/user_proj_example_178/HI
mprj/user_proj_example_179/HI
mprj/user_proj_example_180/HI
mprj/user_proj_example_181/HI
mprj/user_proj_example_182/HI
mprj/user_proj_example_183/HI
mprj/user_proj_example_184/HI
mprj/user_proj_example_185/HI
mprj/user_proj_example_186/HI
mprj/user_proj_example_187/HI
mprj/user_proj_example_188/HI
mprj/user_proj_example_189/HI
mprj/user_proj_example_190/HI
mprj/user_proj_example_191/HI
mprj/user_proj_example_192/HI
mprj/user_proj_example_193/HI
mprj/user_proj_example_194/HI
mprj/user_proj_example_195/HI
mprj/user_proj_example_196/HI
mprj/user_proj_example_197/HI
mprj/user_proj_example_198/HI
mprj/user_proj_example_199/HI
mprj/user_proj_example_200/HI
mprj/user_proj_example_201/HI
mprj/user_proj_example_202/HI
mprj/user_proj_example_203/HI
mprj/user_proj_example_204/HI
mprj/user_proj_example_205/HI
mprj/user_proj_example_206/HI
mprj/user_proj_example_207/HI
mprj/user_proj_example_208/HI
mprj/user_proj_example_209/HI
mprj/user_proj_example_210/HI
mprj/user_proj_example_211/HI
mprj/user_proj_example_212/HI
mprj/user_proj_example_213/HI
mprj/user_proj_example_214/HI
mprj/user_proj_example_215/HI
mprj/user_proj_example_216/HI
mprj/user_proj_example_217/HI
mprj/user_proj_example_218/HI
mprj/user_proj_example_219/HI
mprj/user_proj_example_220/HI
mprj/user_proj_example_221/HI
mprj/user_proj_example_222/HI
mprj/user_proj_example_223/HI
mprj/user_proj_example_224/HI
mprj/user_proj_example_225/HI
mprj/user_proj_example_226/HI
mprj/user_proj_example_227/HI
mprj/user_proj_example_228/HI
mprj/user_proj_example_229/HI
mprj/user_proj_example_230/HI
mprj/user_proj_example_231/HI
mprj/user_proj_example_232/HI
mprj/user_proj_example_233/HI
mprj/user_proj_example_234/HI
mprj/user_proj_example_235/HI
mprj/user_proj_example_236/HI
mprj/user_proj_example_237/HI
mprj/user_proj_example_238/HI
mprj/user_proj_example_239/HI
mprj/user_proj_example_240/HI
mprj/user_proj_example_241/HI
mprj/user_proj_example_242/HI
mprj/user_proj_example_243/HI
mprj/user_proj_example_244/HI
mprj/user_proj_example_245/HI
mprj/user_proj_example_246/HI
mprj/user_proj_example_247/HI
mprj/user_proj_example_248/HI
mprj/user_proj_example_249/HI
mprj/user_proj_example_250/HI
mprj/user_proj_example_251/HI
mprj/user_proj_example_252/HI
mprj/user_proj_example_253/HI
mprj/user_proj_example_254/HI
mprj/user_proj_example_255/HI
mprj/user_proj_example_256/HI
mprj/user_proj_example_257/HI
mprj/user_proj_example_258/HI
mprj/user_proj_example_259/HI
mprj/user_proj_example_260/HI
mprj/user_proj_example_261/HI
mprj/user_proj_example_262/HI
mprj/user_proj_example_263/HI
mprj/user_proj_example_264/HI
mprj/user_proj_example_265/HI
mprj/user_proj_example_266/HI
mprj/user_proj_example_267/HI
mprj/user_proj_example_268/HI
mprj/user_proj_example_269/HI
mprj/user_proj_example_270/HI
mprj/user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 31
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 68 input ports missing set_input_delay.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[1]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[2]
io_in[30]
io_in[31]
io_in[32]
io_in[33]
io_in[34]
io_in[35]
io_in[36]
io_in[37]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
user_clock2
Warning: There are 236 unconstrained endpoints.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[16]
io_oeb[17]
io_oeb[18]
io_oeb[19]
io_oeb[1]
io_oeb[20]
io_oeb[21]
io_oeb[22]
io_oeb[23]
io_oeb[24]
io_oeb[25]
io_oeb[26]
io_oeb[27]
io_oeb[28]
io_oeb[29]
io_oeb[2]
io_oeb[30]
io_oeb[31]
io_oeb[32]
io_oeb[33]
io_oeb[34]
io_oeb[35]
io_oeb[36]
io_oeb[37]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[16]
io_out[17]
io_out[18]
io_out[19]
io_out[1]
io_out[20]
io_out[21]
io_out[22]
io_out[23]
io_out[24]
io_out[25]
io_out[26]
io_out[27]
io_out[28]
io_out[29]
io_out[2]
io_out[30]
io_out[31]
io_out[32]
io_out[33]
io_out[34]
io_out[35]
io_out[36]
io_out[37]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
user_irq[0]
user_irq[1]
user_irq[2]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

51
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/clock.rpt Normal file
View File

@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
5.713159 network latency mprj/_328_/CLK
8.719581 network latency mprj/_305_/CLK
---------------
10.363158 14.289581 latency
3.926423 skew
rise -> fall
min max
4.650000 5.570000 source latency
5.803435 network latency mprj/_328_/CLK
8.714643 network latency mprj/_305_/CLK
---------------
10.453435 14.284643 latency
3.831208 skew
fall -> fall
min max
4.650000 5.570000 source latency
5.861610 network latency mprj/_328_/CLK
6.790437 network latency mprj/_305_/CLK
---------------
10.511610 12.360436 latency
1.848827 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 3.59 fmax = 278.22

4396
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/max.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

4278
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/min.rpt Normal file
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File diff suppressed because it is too large Load Diff

18
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/power.rpt Normal file
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@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 4.252898e-05 3.918598e-05 7.394261e-10 8.171570e-05 13.3%
Combinational 1.180448e-04 3.216421e-04 1.315145e-08 4.397001e-04 71.8%
Clock 3.452346e-05 5.678719e-05 5.304953e-09 9.131595e-05 14.9%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.950972e-04 4.176152e-04 1.919599e-08 6.127317e-04 100.0%
31.8% 68.2% 0.0%

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/skew.max.rpt Normal file
View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
Clock clk
8.719556 source latency mprj/_296_/CLK ^
-5.713159 target latency mprj/_328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.256397 setup skew

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/skew.min.rpt Normal file
View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= min_ff_n40C_1v95 Corner ===================================
Clock clk
5.715373 source latency mprj/_306_/CLK ^
-6.639851 target latency mprj/_312_/CLK ^
-0.250000 clock uncertainty
-0.920002 CRPR
--------------
-2.094481 hold skew

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/tns.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
min_ff_n40C_1v95: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/tns.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
min_ff_n40C_1v95: 0.0

0
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/unpropagated.rpt Normal file
View File

4
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/violator_list.rpt Normal file
View File

@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/wns.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
min_ff_n40C_1v95: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/wns.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
min_ff_n40C_1v95: 0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/ws.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
min_ff_n40C_1v95: 8.453748162997176

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ff_n40C_1v95/ws.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
min_ff_n40C_1v95: 0.3004605538303306

654
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/checks.rpt Normal file
View File

@@ -0,0 +1,654 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= min_ss_100C_1v60 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: mprj/_305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 ^ input external delay
2 0.025451 0.000000 0.000000 18.070000 ^ wb_rst_i (in)
wb_rst_i (net)
0.000868 0.000433 18.070433 ^ mprj/input37/A (sky130_fd_sc_hd__buf_4)
3 0.099860 0.439277 0.431349 18.501781 ^ mprj/input37/X (sky130_fd_sc_hd__buf_4)
mprj/net37 (net)
0.442144 0.028844 18.530626 ^ mprj/_153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.004786 0.108083 0.206681 18.737307 v mprj/_153_/Y (sky130_fd_sc_hd__a21oi_4)
mprj/_039_ (net)
0.108083 0.000092 18.737400 v mprj/hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004346 0.123835 1.167578 19.904978 v mprj/hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net324 (net)
0.123835 0.000076 19.905054 v mprj/hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.057596 0.555790 1.599441 21.504496 v mprj/hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net282 (net)
0.555790 0.001743 21.506237 v mprj/hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.040745 0.416333 1.701606 23.207844 v mprj/hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net325 (net)
0.416333 0.000517 23.208361 v mprj/_160_/A (sky130_fd_sc_hd__nand2_2)
2 0.014913 0.182853 0.298957 23.507318 ^ mprj/_160_/Y (sky130_fd_sc_hd__nand2_2)
mprj/_044_ (net)
0.182853 0.000773 23.508091 ^ mprj/hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.045904 0.695979 1.558522 25.066612 ^ mprj/hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net326 (net)
0.695979 0.001384 25.067997 ^ mprj/fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.131531 0.413820 0.641734 25.709730 ^ mprj/fanout124/X (sky130_fd_sc_hd__buf_6)
mprj/net124 (net)
0.413822 0.000828 25.710558 ^ mprj/_161_/A (sky130_fd_sc_hd__inv_2)
2 0.006802 0.092105 0.169885 25.880444 v mprj/_161_/Y (sky130_fd_sc_hd__inv_2)
mprj/_000_ (net)
0.092105 0.000046 25.880489 v mprj/_233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002145 0.067688 0.433655 26.314144 v mprj/_233_/X (sky130_fd_sc_hd__a32o_1)
mprj/_009_ (net)
0.067688 0.000012 26.314157 v mprj/hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002095 0.101935 1.110495 27.424652 v mprj/hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net431 (net)
0.101935 0.000021 27.424673 v mprj/hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002585 0.103909 1.134758 28.559431 v mprj/hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net315 (net)
0.103909 0.000030 28.559462 v mprj/hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.001834 0.098867 1.122999 29.682461 v mprj/hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net432 (net)
0.098867 0.000016 29.682476 v mprj/_305_/D (sky130_fd_sc_hd__dfxtp_4)
29.682476 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.046052 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.616724 0.003363 29.653362 ^ mprj/wire3/A (sky130_fd_sc_hd__buf_4)
3 0.043881 0.208071 0.537085 30.190447 ^ mprj/wire3/X (sky130_fd_sc_hd__buf_4)
mprj/net274 (net)
0.208231 0.005318 30.195765 ^ mprj/wire2/A (sky130_fd_sc_hd__buf_6)
3 0.098501 0.312768 0.421267 30.617031 ^ mprj/wire2/X (sky130_fd_sc_hd__buf_6)
mprj/net273 (net)
0.313039 0.006011 30.623043 ^ mprj/_155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.050135 0.697929 0.799332 31.422375 ^ mprj/_155_/X (sky130_fd_sc_hd__mux2_1)
mprj/clk (net)
0.697929 0.001894 31.424269 ^ mprj/wire1/A (sky130_fd_sc_hd__buf_4)
3 0.046833 0.221061 0.568903 31.993172 ^ mprj/wire1/X (sky130_fd_sc_hd__buf_4)
mprj/net272 (net)
0.221218 0.005492 31.998665 ^ mprj/clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.091298 0.163726 0.373870 32.372536 ^ mprj/clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_0_clk (net)
0.163845 0.004135 32.376671 ^ mprj/clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.062250 0.123517 0.316668 32.693336 ^ mprj/clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_2_2__leaf_clk (net)
0.123902 0.004572 32.697910 ^ mprj/_305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 32.447906 clock uncertainty
0.000000 32.447906 clock reconvergence pessimism
-0.270404 32.177505 library setup time
32.177505 data required time
---------------------------------------------------------------------------------------------
32.177505 data required time
-29.682476 data arrival time
---------------------------------------------------------------------------------------------
2.495028 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
mprj/fanout124/X 10 33 -23 (VIOLATED)
mprj/fanout125/X 10 33 -23 (VIOLATED)
mprj/_159_/Y 10 29 -19 (VIOLATED)
mprj/_156_/X 10 27 -17 (VIOLATED)
mprj/_195_/X 10 23 -13 (VIOLATED)
mprj/_182_/X 10 21 -11 (VIOLATED)
mprj/clkbuf_2_2__f_clk/X 10 21 -11 (VIOLATED)
mprj/_176_/Y 10 19 -9 (VIOLATED)
mprj/_297_/Q 10 19 -9 (VIOLATED)
mprj/clkbuf_2_1__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_3__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_0__f_clk/X 10 17 -7 (VIOLATED)
mprj/hold140/X 10 17 -7 (VIOLATED)
mprj/wire4/X 10 17 -7 (VIOLATED)
mprj/_157_/Y 10 15 -5 (VIOLATED)
mprj/_298_/Q 10 15 -5 (VIOLATED)
mprj/_301_/Q 10 15 -5 (VIOLATED)
mprj/_305_/Q 10 15 -5 (VIOLATED)
mprj/hold8/X 10 15 -5 (VIOLATED)
mprj/_228_/X 10 13 -3 (VIOLATED)
mprj/_299_/Q 10 13 -3 (VIOLATED)
mprj/_302_/Q 10 13 -3 (VIOLATED)
mprj/_303_/Q 10 13 -3 (VIOLATED)
mprj/_309_/Q 10 13 -3 (VIOLATED)
mprj/_311_/Q 10 13 -3 (VIOLATED)
mprj/_158_/Y 10 11 (VIOLATED)
mprj/_175_/X 10 11 (VIOLATED)
mprj/_300_/Q 10 11 (VIOLATED)
mprj/_308_/Q 10 11 (VIOLATED)
mprj/_310_/Q 10 11 (VIOLATED)
mprj/_312_/Q 10 11 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 186 unannotated drivers.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[8]
io_in[9]
user_clock2
mprj/clkload0/X
mprj/clkload1/X
mprj/clkload2/X
mprj/user_proj_example_141/HI
mprj/user_proj_example_142/HI
mprj/user_proj_example_143/HI
mprj/user_proj_example_144/HI
mprj/user_proj_example_145/HI
mprj/user_proj_example_146/HI
mprj/user_proj_example_147/HI
mprj/user_proj_example_148/HI
mprj/user_proj_example_149/HI
mprj/user_proj_example_150/HI
mprj/user_proj_example_151/HI
mprj/user_proj_example_152/HI
mprj/user_proj_example_153/HI
mprj/user_proj_example_154/HI
mprj/user_proj_example_155/HI
mprj/user_proj_example_156/HI
mprj/user_proj_example_157/HI
mprj/user_proj_example_158/HI
mprj/user_proj_example_159/HI
mprj/user_proj_example_160/HI
mprj/user_proj_example_161/HI
mprj/user_proj_example_162/HI
mprj/user_proj_example_163/HI
mprj/user_proj_example_164/HI
mprj/user_proj_example_165/HI
mprj/user_proj_example_166/HI
mprj/user_proj_example_167/HI
mprj/user_proj_example_168/HI
mprj/user_proj_example_169/HI
mprj/user_proj_example_170/HI
mprj/user_proj_example_171/HI
mprj/user_proj_example_172/HI
mprj/user_proj_example_173/HI
mprj/user_proj_example_174/HI
mprj/user_proj_example_175/HI
mprj/user_proj_example_176/HI
mprj/user_proj_example_177/HI
mprj/user_proj_example_178/HI
mprj/user_proj_example_179/HI
mprj/user_proj_example_180/HI
mprj/user_proj_example_181/HI
mprj/user_proj_example_182/HI
mprj/user_proj_example_183/HI
mprj/user_proj_example_184/HI
mprj/user_proj_example_185/HI
mprj/user_proj_example_186/HI
mprj/user_proj_example_187/HI
mprj/user_proj_example_188/HI
mprj/user_proj_example_189/HI
mprj/user_proj_example_190/HI
mprj/user_proj_example_191/HI
mprj/user_proj_example_192/HI
mprj/user_proj_example_193/HI
mprj/user_proj_example_194/HI
mprj/user_proj_example_195/HI
mprj/user_proj_example_196/HI
mprj/user_proj_example_197/HI
mprj/user_proj_example_198/HI
mprj/user_proj_example_199/HI
mprj/user_proj_example_200/HI
mprj/user_proj_example_201/HI
mprj/user_proj_example_202/HI
mprj/user_proj_example_203/HI
mprj/user_proj_example_204/HI
mprj/user_proj_example_205/HI
mprj/user_proj_example_206/HI
mprj/user_proj_example_207/HI
mprj/user_proj_example_208/HI
mprj/user_proj_example_209/HI
mprj/user_proj_example_210/HI
mprj/user_proj_example_211/HI
mprj/user_proj_example_212/HI
mprj/user_proj_example_213/HI
mprj/user_proj_example_214/HI
mprj/user_proj_example_215/HI
mprj/user_proj_example_216/HI
mprj/user_proj_example_217/HI
mprj/user_proj_example_218/HI
mprj/user_proj_example_219/HI
mprj/user_proj_example_220/HI
mprj/user_proj_example_221/HI
mprj/user_proj_example_222/HI
mprj/user_proj_example_223/HI
mprj/user_proj_example_224/HI
mprj/user_proj_example_225/HI
mprj/user_proj_example_226/HI
mprj/user_proj_example_227/HI
mprj/user_proj_example_228/HI
mprj/user_proj_example_229/HI
mprj/user_proj_example_230/HI
mprj/user_proj_example_231/HI
mprj/user_proj_example_232/HI
mprj/user_proj_example_233/HI
mprj/user_proj_example_234/HI
mprj/user_proj_example_235/HI
mprj/user_proj_example_236/HI
mprj/user_proj_example_237/HI
mprj/user_proj_example_238/HI
mprj/user_proj_example_239/HI
mprj/user_proj_example_240/HI
mprj/user_proj_example_241/HI
mprj/user_proj_example_242/HI
mprj/user_proj_example_243/HI
mprj/user_proj_example_244/HI
mprj/user_proj_example_245/HI
mprj/user_proj_example_246/HI
mprj/user_proj_example_247/HI
mprj/user_proj_example_248/HI
mprj/user_proj_example_249/HI
mprj/user_proj_example_250/HI
mprj/user_proj_example_251/HI
mprj/user_proj_example_252/HI
mprj/user_proj_example_253/HI
mprj/user_proj_example_254/HI
mprj/user_proj_example_255/HI
mprj/user_proj_example_256/HI
mprj/user_proj_example_257/HI
mprj/user_proj_example_258/HI
mprj/user_proj_example_259/HI
mprj/user_proj_example_260/HI
mprj/user_proj_example_261/HI
mprj/user_proj_example_262/HI
mprj/user_proj_example_263/HI
mprj/user_proj_example_264/HI
mprj/user_proj_example_265/HI
mprj/user_proj_example_266/HI
mprj/user_proj_example_267/HI
mprj/user_proj_example_268/HI
mprj/user_proj_example_269/HI
mprj/user_proj_example_270/HI
mprj/user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 31
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 68 input ports missing set_input_delay.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[1]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[2]
io_in[30]
io_in[31]
io_in[32]
io_in[33]
io_in[34]
io_in[35]
io_in[36]
io_in[37]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
user_clock2
Warning: There are 236 unconstrained endpoints.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[16]
io_oeb[17]
io_oeb[18]
io_oeb[19]
io_oeb[1]
io_oeb[20]
io_oeb[21]
io_oeb[22]
io_oeb[23]
io_oeb[24]
io_oeb[25]
io_oeb[26]
io_oeb[27]
io_oeb[28]
io_oeb[29]
io_oeb[2]
io_oeb[30]
io_oeb[31]
io_oeb[32]
io_oeb[33]
io_oeb[34]
io_oeb[35]
io_oeb[36]
io_oeb[37]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[16]
io_out[17]
io_out[18]
io_out[19]
io_out[1]
io_out[20]
io_out[21]
io_out[22]
io_out[23]
io_out[24]
io_out[25]
io_out[26]
io_out[27]
io_out[28]
io_out[29]
io_out[2]
io_out[30]
io_out[31]
io_out[32]
io_out[33]
io_out[34]
io_out[35]
io_out[36]
io_out[37]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
la_data_out[66]
la_data_out[67]
la_data_out[68]
la_data_out[69]
la_data_out[70]
la_data_out[71]
la_data_out[72]
la_data_out[73]
la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
user_irq[0]
user_irq[1]
user_irq[2]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

51
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/clock.rpt Normal file
View File

@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
7.501005 network latency mprj/_328_/CLK
10.471915 network latency mprj/_305_/CLK
---------------
12.151006 16.041914 latency
3.890909 skew
rise -> fall
min max
4.650000 5.570000 source latency
7.592703 network latency mprj/_328_/CLK
10.682340 network latency mprj/_305_/CLK
---------------
12.242703 16.252340 latency
4.009637 skew
fall -> fall
min max
4.650000 5.570000 source latency
7.866813 network latency mprj/_328_/CLK
8.796917 network latency mprj/_305_/CLK
---------------
12.516813 14.366917 latency
1.850104 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 10.63 fmax = 94.10

4396
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/max.rpt Normal file
View File

File diff suppressed because it is too large Load Diff

4242
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/min.rpt Normal file
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File diff suppressed because it is too large Load Diff

18
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/power.rpt Normal file
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@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 2.904808e-05 2.633182e-05 5.104404e-07 5.589034e-05 13.3%
Combinational 8.208605e-05 2.163509e-04 3.839341e-06 3.022763e-04 71.7%
Clock 2.461669e-05 3.840392e-05 1.530292e-07 6.317364e-05 15.0%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.357508e-04 2.810867e-04 4.502832e-06 4.213403e-04 100.0%
32.2% 66.7% 1.1%

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/skew.max.rpt Normal file
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@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
Clock clk
10.471891 source latency mprj/_296_/CLK ^
-7.686064 target latency mprj/_328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.035827 setup skew

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/skew.min.rpt Normal file
View File

@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= min_ss_100C_1v60 Corner ===================================
Clock clk
7.691626 source latency mprj/_306_/CLK ^
-8.616487 target latency mprj/_312_/CLK ^
-0.250000 clock uncertainty
-0.920388 CRPR
--------------
-2.095248 hold skew

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/tns.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
min_ss_100C_1v60: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/tns.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
min_ss_100C_1v60: 0.0

0
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/unpropagated.rpt Normal file
View File

4
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/violator_list.rpt Normal file
View File

@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/wns.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
min_ss_100C_1v60: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/wns.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
min_ss_100C_1v60: 0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/ws.max.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
min_ss_100C_1v60: 2.495028254621664

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_ss_100C_1v60/ws.min.rpt Normal file
View File

@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
min_ss_100C_1v60: 1.14169033014592

654
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/checks.rpt Normal file
View File

@@ -0,0 +1,654 @@
===========================================================================
report_checks -unconstrained
===========================================================================
======================= min_tt_025C_1v80 Corner ===================================
Startpoint: wb_rst_i (input port clocked by clk)
Endpoint: mprj/_305_ (rising edge-triggered flip-flop clocked by clk)
Path Group: clk
Path Type: max
Fanout Cap Slew Delay Time Description
---------------------------------------------------------------------------------------------
0.000000 0.000000 clock clk (rise edge)
5.570000 5.570000 clock network delay (propagated)
12.500000 18.070000 ^ input external delay
2 0.025357 0.000000 0.000000 18.070000 ^ wb_rst_i (in)
wb_rst_i (net)
0.000864 0.000432 18.070431 ^ mprj/input37/A (sky130_fd_sc_hd__buf_4)
3 0.099660 0.276812 0.248303 18.318733 ^ mprj/input37/X (sky130_fd_sc_hd__buf_4)
mprj/net37 (net)
0.281440 0.028603 18.347336 ^ mprj/_153_/A1 (sky130_fd_sc_hd__a21oi_4)
1 0.004837 0.066351 0.083245 18.430582 v mprj/_153_/Y (sky130_fd_sc_hd__a21oi_4)
mprj/_039_ (net)
0.066351 0.000092 18.430674 v mprj/hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.004397 0.060437 0.569260 18.999935 v mprj/hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net324 (net)
0.060437 0.000078 19.000013 v mprj/hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
15 0.056936 0.288685 0.785850 19.785862 v mprj/hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net282 (net)
0.288693 0.001723 19.787586 v mprj/hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
7 0.040279 0.215661 0.826933 20.614519 v mprj/hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net325 (net)
0.215661 0.000512 20.615030 v mprj/_160_/A (sky130_fd_sc_hd__nand2_2)
2 0.014904 0.105932 0.163373 20.778404 ^ mprj/_160_/Y (sky130_fd_sc_hd__nand2_2)
mprj/_044_ (net)
0.105936 0.000773 20.779177 ^ mprj/hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
5 0.045784 0.449853 0.847871 21.627047 ^ mprj/hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net326 (net)
0.449853 0.001377 21.628424 ^ mprj/fanout124/A (sky130_fd_sc_hd__buf_6)
33 0.132205 0.264068 0.320350 21.948774 ^ mprj/fanout124/X (sky130_fd_sc_hd__buf_6)
mprj/net124 (net)
0.264072 0.000833 21.949608 ^ mprj/_161_/A (sky130_fd_sc_hd__inv_2)
2 0.006861 0.057027 0.065860 22.015467 v mprj/_161_/Y (sky130_fd_sc_hd__inv_2)
mprj/_000_ (net)
0.057027 0.000046 22.015514 v mprj/_233_/A2 (sky130_fd_sc_hd__a32o_1)
1 0.002196 0.038286 0.238582 22.254097 v mprj/_233_/X (sky130_fd_sc_hd__a32o_1)
mprj/_009_ (net)
0.038286 0.000012 22.254108 v mprj/hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002146 0.049763 0.539636 22.793745 v mprj/hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net431 (net)
0.049763 0.000021 22.793766 v mprj/hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.002636 0.051992 0.548550 23.342316 v mprj/hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net315 (net)
0.051992 0.000030 23.342346 v mprj/hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
1 0.001933 0.048629 0.543027 23.885372 v mprj/hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
mprj/net432 (net)
0.048629 0.000018 23.885391 v mprj/_305_/D (sky130_fd_sc_hd__dfxtp_4)
23.885391 data arrival time
25.000000 25.000000 clock clk (rise edge)
4.650000 29.650000 clock source latency
2 0.045958 0.610000 0.000000 29.650000 ^ wb_clk_i (in)
wb_clk_i (net)
0.616693 0.003347 29.653345 ^ mprj/wire3/A (sky130_fd_sc_hd__buf_4)
3 0.043704 0.132282 0.295669 29.949015 ^ mprj/wire3/X (sky130_fd_sc_hd__buf_4)
mprj/net274 (net)
0.132688 0.005294 29.954308 ^ mprj/wire2/A (sky130_fd_sc_hd__buf_6)
3 0.098359 0.197490 0.236511 30.190819 ^ mprj/wire2/X (sky130_fd_sc_hd__buf_6)
mprj/net273 (net)
0.197760 0.006004 30.196823 ^ mprj/_155_/A1 (sky130_fd_sc_hd__mux2_1)
3 0.049934 0.437838 0.451490 30.648314 ^ mprj/_155_/X (sky130_fd_sc_hd__mux2_1)
mprj/clk (net)
0.437849 0.001894 30.650208 ^ mprj/wire1/A (sky130_fd_sc_hd__buf_4)
3 0.046619 0.138052 0.273211 30.923418 ^ mprj/wire1/X (sky130_fd_sc_hd__buf_4)
mprj/net272 (net)
0.138379 0.005464 30.928883 ^ mprj/clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
9 0.090763 0.107644 0.211031 31.139914 ^ mprj/clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_0_clk (net)
0.107883 0.004100 31.144012 ^ mprj/clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
21 0.062247 0.080381 0.180286 31.324299 ^ mprj/clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
mprj/clknet_2_2__leaf_clk (net)
0.080802 0.004576 31.328875 ^ mprj/_305_/CLK (sky130_fd_sc_hd__dfxtp_4)
-0.250000 31.078875 clock uncertainty
0.000000 31.078875 clock reconvergence pessimism
-0.105396 30.973478 library setup time
30.973478 data required time
---------------------------------------------------------------------------------------------
30.973478 data required time
-23.885391 data arrival time
---------------------------------------------------------------------------------------------
7.088089 slack (MET)
===========================================================================
report_checks --slack_max -0.01
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
No paths found.
===========================================================================
report_check_types -max_slew -max_cap -max_fanout -violators
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
max fanout
Pin Limit Fanout Slack
---------------------------------------------------------
mprj/fanout124/X 10 33 -23 (VIOLATED)
mprj/fanout125/X 10 33 -23 (VIOLATED)
mprj/_159_/Y 10 29 -19 (VIOLATED)
mprj/_156_/X 10 27 -17 (VIOLATED)
mprj/_195_/X 10 23 -13 (VIOLATED)
mprj/_182_/X 10 21 -11 (VIOLATED)
mprj/clkbuf_2_2__f_clk/X 10 21 -11 (VIOLATED)
mprj/_176_/Y 10 19 -9 (VIOLATED)
mprj/_297_/Q 10 19 -9 (VIOLATED)
mprj/clkbuf_2_1__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_3__f_clk/X 10 19 -9 (VIOLATED)
mprj/clkbuf_2_0__f_clk/X 10 17 -7 (VIOLATED)
mprj/hold140/X 10 17 -7 (VIOLATED)
mprj/wire4/X 10 17 -7 (VIOLATED)
mprj/_157_/Y 10 15 -5 (VIOLATED)
mprj/_298_/Q 10 15 -5 (VIOLATED)
mprj/_301_/Q 10 15 -5 (VIOLATED)
mprj/_305_/Q 10 15 -5 (VIOLATED)
mprj/hold8/X 10 15 -5 (VIOLATED)
mprj/_228_/X 10 13 -3 (VIOLATED)
mprj/_299_/Q 10 13 -3 (VIOLATED)
mprj/_302_/Q 10 13 -3 (VIOLATED)
mprj/_303_/Q 10 13 -3 (VIOLATED)
mprj/_309_/Q 10 13 -3 (VIOLATED)
mprj/_311_/Q 10 13 -3 (VIOLATED)
mprj/_158_/Y 10 11 (VIOLATED)
mprj/_175_/X 10 11 (VIOLATED)
mprj/_300_/Q 10 11 (VIOLATED)
mprj/_308_/Q 10 11 (VIOLATED)
mprj/_310_/Q 10 11 (VIOLATED)
mprj/_312_/Q 10 11 (VIOLATED)
===========================================================================
report_parasitic_annotation -report_unannotated
============================================================================
Found 186 unannotated drivers.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[8]
io_in[9]
user_clock2
mprj/clkload0/X
mprj/clkload1/X
mprj/clkload2/X
mprj/user_proj_example_141/HI
mprj/user_proj_example_142/HI
mprj/user_proj_example_143/HI
mprj/user_proj_example_144/HI
mprj/user_proj_example_145/HI
mprj/user_proj_example_146/HI
mprj/user_proj_example_147/HI
mprj/user_proj_example_148/HI
mprj/user_proj_example_149/HI
mprj/user_proj_example_150/HI
mprj/user_proj_example_151/HI
mprj/user_proj_example_152/HI
mprj/user_proj_example_153/HI
mprj/user_proj_example_154/HI
mprj/user_proj_example_155/HI
mprj/user_proj_example_156/HI
mprj/user_proj_example_157/HI
mprj/user_proj_example_158/HI
mprj/user_proj_example_159/HI
mprj/user_proj_example_160/HI
mprj/user_proj_example_161/HI
mprj/user_proj_example_162/HI
mprj/user_proj_example_163/HI
mprj/user_proj_example_164/HI
mprj/user_proj_example_165/HI
mprj/user_proj_example_166/HI
mprj/user_proj_example_167/HI
mprj/user_proj_example_168/HI
mprj/user_proj_example_169/HI
mprj/user_proj_example_170/HI
mprj/user_proj_example_171/HI
mprj/user_proj_example_172/HI
mprj/user_proj_example_173/HI
mprj/user_proj_example_174/HI
mprj/user_proj_example_175/HI
mprj/user_proj_example_176/HI
mprj/user_proj_example_177/HI
mprj/user_proj_example_178/HI
mprj/user_proj_example_179/HI
mprj/user_proj_example_180/HI
mprj/user_proj_example_181/HI
mprj/user_proj_example_182/HI
mprj/user_proj_example_183/HI
mprj/user_proj_example_184/HI
mprj/user_proj_example_185/HI
mprj/user_proj_example_186/HI
mprj/user_proj_example_187/HI
mprj/user_proj_example_188/HI
mprj/user_proj_example_189/HI
mprj/user_proj_example_190/HI
mprj/user_proj_example_191/HI
mprj/user_proj_example_192/HI
mprj/user_proj_example_193/HI
mprj/user_proj_example_194/HI
mprj/user_proj_example_195/HI
mprj/user_proj_example_196/HI
mprj/user_proj_example_197/HI
mprj/user_proj_example_198/HI
mprj/user_proj_example_199/HI
mprj/user_proj_example_200/HI
mprj/user_proj_example_201/HI
mprj/user_proj_example_202/HI
mprj/user_proj_example_203/HI
mprj/user_proj_example_204/HI
mprj/user_proj_example_205/HI
mprj/user_proj_example_206/HI
mprj/user_proj_example_207/HI
mprj/user_proj_example_208/HI
mprj/user_proj_example_209/HI
mprj/user_proj_example_210/HI
mprj/user_proj_example_211/HI
mprj/user_proj_example_212/HI
mprj/user_proj_example_213/HI
mprj/user_proj_example_214/HI
mprj/user_proj_example_215/HI
mprj/user_proj_example_216/HI
mprj/user_proj_example_217/HI
mprj/user_proj_example_218/HI
mprj/user_proj_example_219/HI
mprj/user_proj_example_220/HI
mprj/user_proj_example_221/HI
mprj/user_proj_example_222/HI
mprj/user_proj_example_223/HI
mprj/user_proj_example_224/HI
mprj/user_proj_example_225/HI
mprj/user_proj_example_226/HI
mprj/user_proj_example_227/HI
mprj/user_proj_example_228/HI
mprj/user_proj_example_229/HI
mprj/user_proj_example_230/HI
mprj/user_proj_example_231/HI
mprj/user_proj_example_232/HI
mprj/user_proj_example_233/HI
mprj/user_proj_example_234/HI
mprj/user_proj_example_235/HI
mprj/user_proj_example_236/HI
mprj/user_proj_example_237/HI
mprj/user_proj_example_238/HI
mprj/user_proj_example_239/HI
mprj/user_proj_example_240/HI
mprj/user_proj_example_241/HI
mprj/user_proj_example_242/HI
mprj/user_proj_example_243/HI
mprj/user_proj_example_244/HI
mprj/user_proj_example_245/HI
mprj/user_proj_example_246/HI
mprj/user_proj_example_247/HI
mprj/user_proj_example_248/HI
mprj/user_proj_example_249/HI
mprj/user_proj_example_250/HI
mprj/user_proj_example_251/HI
mprj/user_proj_example_252/HI
mprj/user_proj_example_253/HI
mprj/user_proj_example_254/HI
mprj/user_proj_example_255/HI
mprj/user_proj_example_256/HI
mprj/user_proj_example_257/HI
mprj/user_proj_example_258/HI
mprj/user_proj_example_259/HI
mprj/user_proj_example_260/HI
mprj/user_proj_example_261/HI
mprj/user_proj_example_262/HI
mprj/user_proj_example_263/HI
mprj/user_proj_example_264/HI
mprj/user_proj_example_265/HI
mprj/user_proj_example_266/HI
mprj/user_proj_example_267/HI
mprj/user_proj_example_268/HI
mprj/user_proj_example_269/HI
mprj/user_proj_example_270/HI
mprj/user_proj_example_271/HI
Found 0 partially unannotated drivers.
===========================================================================
max slew violation count 0
max fanout violation count 31
max cap violation count 0
============================================================================
===========================================================================
check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
===========================================================================
Warning: There are 68 input ports missing set_input_delay.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_in[0]
io_in[10]
io_in[11]
io_in[12]
io_in[13]
io_in[14]
io_in[15]
io_in[16]
io_in[17]
io_in[18]
io_in[19]
io_in[1]
io_in[20]
io_in[21]
io_in[22]
io_in[23]
io_in[24]
io_in[25]
io_in[26]
io_in[27]
io_in[28]
io_in[29]
io_in[2]
io_in[30]
io_in[31]
io_in[32]
io_in[33]
io_in[34]
io_in[35]
io_in[36]
io_in[37]
io_in[3]
io_in[4]
io_in[5]
io_in[6]
io_in[7]
io_in[8]
io_in[9]
user_clock2
Warning: There are 236 unconstrained endpoints.
analog_io[0]
analog_io[10]
analog_io[11]
analog_io[12]
analog_io[13]
analog_io[14]
analog_io[15]
analog_io[16]
analog_io[17]
analog_io[18]
analog_io[19]
analog_io[1]
analog_io[20]
analog_io[21]
analog_io[22]
analog_io[23]
analog_io[24]
analog_io[25]
analog_io[26]
analog_io[27]
analog_io[28]
analog_io[2]
analog_io[3]
analog_io[4]
analog_io[5]
analog_io[6]
analog_io[7]
analog_io[8]
analog_io[9]
io_oeb[0]
io_oeb[10]
io_oeb[11]
io_oeb[12]
io_oeb[13]
io_oeb[14]
io_oeb[15]
io_oeb[16]
io_oeb[17]
io_oeb[18]
io_oeb[19]
io_oeb[1]
io_oeb[20]
io_oeb[21]
io_oeb[22]
io_oeb[23]
io_oeb[24]
io_oeb[25]
io_oeb[26]
io_oeb[27]
io_oeb[28]
io_oeb[29]
io_oeb[2]
io_oeb[30]
io_oeb[31]
io_oeb[32]
io_oeb[33]
io_oeb[34]
io_oeb[35]
io_oeb[36]
io_oeb[37]
io_oeb[3]
io_oeb[4]
io_oeb[5]
io_oeb[6]
io_oeb[7]
io_oeb[8]
io_oeb[9]
io_out[0]
io_out[10]
io_out[11]
io_out[12]
io_out[13]
io_out[14]
io_out[15]
io_out[16]
io_out[17]
io_out[18]
io_out[19]
io_out[1]
io_out[20]
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io_out[23]
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io_out[25]
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io_out[2]
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io_out[37]
io_out[3]
io_out[4]
io_out[5]
io_out[6]
io_out[7]
io_out[8]
io_out[9]
la_data_out[100]
la_data_out[101]
la_data_out[102]
la_data_out[103]
la_data_out[104]
la_data_out[105]
la_data_out[106]
la_data_out[107]
la_data_out[108]
la_data_out[109]
la_data_out[110]
la_data_out[111]
la_data_out[112]
la_data_out[113]
la_data_out[114]
la_data_out[115]
la_data_out[116]
la_data_out[117]
la_data_out[118]
la_data_out[119]
la_data_out[120]
la_data_out[121]
la_data_out[122]
la_data_out[123]
la_data_out[124]
la_data_out[125]
la_data_out[126]
la_data_out[127]
la_data_out[16]
la_data_out[17]
la_data_out[18]
la_data_out[19]
la_data_out[20]
la_data_out[21]
la_data_out[22]
la_data_out[23]
la_data_out[24]
la_data_out[25]
la_data_out[26]
la_data_out[27]
la_data_out[28]
la_data_out[29]
la_data_out[30]
la_data_out[31]
la_data_out[32]
la_data_out[33]
la_data_out[34]
la_data_out[35]
la_data_out[36]
la_data_out[37]
la_data_out[38]
la_data_out[39]
la_data_out[40]
la_data_out[41]
la_data_out[42]
la_data_out[43]
la_data_out[44]
la_data_out[45]
la_data_out[46]
la_data_out[47]
la_data_out[48]
la_data_out[49]
la_data_out[50]
la_data_out[51]
la_data_out[52]
la_data_out[53]
la_data_out[54]
la_data_out[55]
la_data_out[56]
la_data_out[57]
la_data_out[58]
la_data_out[59]
la_data_out[60]
la_data_out[61]
la_data_out[62]
la_data_out[63]
la_data_out[64]
la_data_out[65]
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la_data_out[70]
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la_data_out[72]
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la_data_out[74]
la_data_out[75]
la_data_out[76]
la_data_out[77]
la_data_out[78]
la_data_out[79]
la_data_out[80]
la_data_out[81]
la_data_out[82]
la_data_out[83]
la_data_out[84]
la_data_out[85]
la_data_out[86]
la_data_out[87]
la_data_out[88]
la_data_out[89]
la_data_out[90]
la_data_out[91]
la_data_out[92]
la_data_out[93]
la_data_out[94]
la_data_out[95]
la_data_out[96]
la_data_out[97]
la_data_out[98]
la_data_out[99]
user_irq[0]
user_irq[1]
user_irq[2]
wbs_dat_o[16]
wbs_dat_o[17]
wbs_dat_o[18]
wbs_dat_o[19]
wbs_dat_o[20]
wbs_dat_o[21]
wbs_dat_o[22]
wbs_dat_o[23]
wbs_dat_o[24]
wbs_dat_o[25]
wbs_dat_o[26]
wbs_dat_o[27]
wbs_dat_o[28]
wbs_dat_o[29]
wbs_dat_o[30]
wbs_dat_o[31]

51
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/clock.rpt Normal file
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@@ -0,0 +1,51 @@
Clock: clk
Sources: wb_clk_i
Generated: no
Virtual: yes
Propagated: no
Period: 25.000000
===========================================================================
report_clock_properties
============================================================================
Clock Period Waveform
----------------------------------------------------
clk 25.000000 0.000000 12.500000
===========================================================================
report_clock_latency
============================================================================
Clock clk
rise -> rise
min max
4.650000 5.570000 source latency
6.310439 network latency mprj/_328_/CLK
9.235908 network latency mprj/_305_/CLK
---------------
10.960439 14.805908 latency
3.845469 skew
rise -> fall
min max
4.650000 5.570000 source latency
6.292255 network latency mprj/_328_/CLK
9.247598 network latency mprj/_305_/CLK
---------------
10.942255 14.817598 latency
3.875343 skew
fall -> fall
min max
4.650000 5.570000 source latency
6.433867 network latency mprj/_328_/CLK
7.361390 network latency mprj/_305_/CLK
---------------
11.083866 12.931390 latency
1.847523 skew
===========================================================================
report_clock_min_period
============================================================================
clk period_min = 5.39 fmax = 185.54

4396
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/max.rpt Normal file
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File diff suppressed because it is too large Load Diff

4251
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/min.rpt Normal file
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File diff suppressed because it is too large Load Diff

18
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/power.rpt Normal file
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@@ -0,0 +1,18 @@
===========================================================================
report_power
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
Group Internal Switching Leakage Total
Power Power Power Power (Watts)
------------------------------------------------------------------------
Sequential 3.690075e-05 3.338997e-05 2.838373e-10 7.029100e-05 13.4%
Combinational 1.019759e-04 2.739251e-04 3.073229e-09 3.759041e-04 71.6%
Clock 3.011068e-05 4.853097e-05 4.242312e-09 7.864588e-05 15.0%
Macro 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
Pad 0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00 0.0%
------------------------------------------------------------------------
Total 1.689873e-04 3.558461e-04 7.599371e-09 5.248411e-04 100.0%
32.2% 67.8% 0.0%

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/skew.max.rpt Normal file
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@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Setup)
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
Clock clk
9.235883 source latency mprj/_296_/CLK ^
-6.320013 target latency mprj/_328_/CLK ^
0.250000 clock uncertainty
0.000000 CRPR
--------------
3.165870 setup skew

14
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/skew.min.rpt Normal file
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@@ -0,0 +1,14 @@
===========================================================================
Clock Skew (Hold)
============================================================================
======================= min_tt_025C_1v80 Corner ===================================
Clock clk
6.323193 source latency mprj/_306_/CLK ^
-7.247747 target latency mprj/_312_/CLK ^
-0.250000 clock uncertainty
-0.920073 CRPR
--------------
-2.094627 hold skew

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/tns.max.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Setup)
============================================================================
min_tt_025C_1v80: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/tns.min.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Total Negative Slack (Hold)
============================================================================
min_tt_025C_1v80: 0.0

0
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/unpropagated.rpt Normal file
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4
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/violator_list.rpt Normal file
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@@ -0,0 +1,4 @@
===========================================================================
Violator List
============================================================================

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/wns.max.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Setup)
============================================================================
min_tt_025C_1v80: 0.0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/wns.min.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Worst Negative Slack (Hold)
============================================================================
min_tt_025C_1v80: 0

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/ws.max.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Setup)
============================================================================
min_tt_025C_1v80: 7.08808853895645

5
signoff/user_project_wrapper/openlane-signoff/timing-reports/min_tt_025C_1v80/ws.min.rpt Normal file
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@@ -0,0 +1,5 @@
===========================================================================
Worst Slack (Hold)
============================================================================
min_tt_025C_1v80: 0.4135385484433063

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