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32
verilog/dv/la_test1/Makefile
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32
verilog/dv/la_test1/Makefile
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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PWDD := $(shell pwd)
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BLOCKS := $(shell basename $(PWDD))
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# ---- Include Partitioned Makefiles ----
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CONFIG = caravel_user_project
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include $(MCW_ROOT)/verilog/dv/make/env.makefile
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include $(MCW_ROOT)/verilog/dv/make/var.makefile
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include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
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include $(MCW_ROOT)/verilog/dv/make/sim.makefile
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130
verilog/dv/la_test1/la_test1.c
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130
verilog/dv/la_test1/la_test1.c
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/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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*/
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// This include is relative to $CARAVEL_PATH (see Makefile)
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#include <defs.h>
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#include <stub.c>
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// --------------------------------------------------------
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/*
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MPRJ Logic Analyzer Test:
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- Observes counter value through LA probes [31:0]
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- Sets counter initial value through LA probes [63:32]
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- Flags when counter value exceeds 500 through the management SoC gpio
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- Outputs message to the UART when the test concludes successfuly
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*/
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void main()
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{
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int j;
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/* Set up the housekeeping SPI to be connected internally so */
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/* that external pin changes don't affect it. */
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// reg_spi_enable = 1;
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// reg_spimaster_cs = 0x00000;
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// reg_spimaster_control = 0x0801;
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// reg_spimaster_control = 0xa002; // Enable, prescaler = 2,
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// connect to housekeeping SPI
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// Connect the housekeeping SPI to the SPI master
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// so that the CSB line is not left floating. This allows
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// all of the GPIO pins to be used for user functions.
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// The upper GPIO pins are configured to be output
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// and accessble to the management SoC.
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// Used to flad the start/end of a test
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// The lower GPIO pins are configured to be output
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// and accessible to the user project. They show
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// the project count value, although this test is
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// designed to read the project count through the
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// logic analyzer probes.
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// I/O 6 is configured for the UART Tx line
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reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_6 = GPIO_MODE_MGMT_STD_OUTPUT;
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// Set UART clock to 64 kbaud (enable before I/O configuration)
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// reg_uart_clkdiv = 625;
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reg_uart_enable = 1;
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// Now, apply the configuration
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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// Configure LA probes [31:0], [127:64] as inputs to the cpu
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// Configure LA probes [63:32] as outputs from the cpu
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reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
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reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
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reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
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reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
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// Flag start of the test
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reg_mprj_datal = 0xAB400000;
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// Set Counter value to zero through LA probes [63:32]
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reg_la1_data = 0x00000000;
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// Configure LA probes from [63:32] as inputs to disable counter write
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reg_la1_oenb = reg_la1_iena = 0x00000000;
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while (1) {
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if (reg_la0_data_in > 0x1F4) {
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reg_mprj_datal = 0xAB410000;
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break;
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}
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}
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print("\n");
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print("Monitor: Test 1 Passed\n\n"); // Makes simulation very long!
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reg_mprj_datal = 0xAB510000;
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}
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247
verilog/dv/la_test1/la_test1_tb.v
Normal file
247
verilog/dv/la_test1/la_test1_tb.v
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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`timescale 1 ns / 1 ps
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module la_test1_tb;
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reg clock;
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reg RSTB;
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reg CSB;
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reg power1, power2;
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wire gpio;
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wire uart_tx;
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wire [37:0] mprj_io;
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wire [15:0] checkbits;
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assign checkbits = mprj_io[31:16];
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assign uart_tx = mprj_io[6];
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always #12.5 clock <= (clock === 1'b0);
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initial begin
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clock = 0;
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end
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`ifdef ENABLE_SDF
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initial begin
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$sdf_annotate("../../../sdf/user_proj_example.sdf", uut.mprj) ;
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$sdf_annotate("../../../sdf/user_project_wrapper.sdf", uut.mprj.mprj) ;
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$sdf_annotate("../../../mgmt_core_wrapper/sdf/DFFRAM.sdf", uut.soc.DFFRAM_0) ;
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$sdf_annotate("../../../mgmt_core_wrapper/sdf/mgmt_core.sdf", uut.soc.core) ;
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$sdf_annotate("../../../caravel/sdf/housekeeping.sdf", uut.housekeeping) ;
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$sdf_annotate("../../../caravel/sdf/chip_io.sdf", uut.padframe) ;
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$sdf_annotate("../../../caravel/sdf/mprj_logic_high.sdf", uut.mgmt_buffers.mprj_logic_high_inst) ;
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$sdf_annotate("../../../caravel/sdf/mprj2_logic_high.sdf", uut.mgmt_buffers.mprj2_logic_high_inst) ;
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$sdf_annotate("../../../caravel/sdf/mgmt_protect_hv.sdf", uut.mgmt_buffers.powergood_check) ;
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$sdf_annotate("../../../caravel/sdf/mgmt_protect.sdf", uut.mgmt_buffers) ;
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$sdf_annotate("../../../caravel/sdf/caravel_clocking.sdf", uut.clocking) ;
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$sdf_annotate("../../../caravel/sdf/digital_pll.sdf", uut.pll) ;
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$sdf_annotate("../../../caravel/sdf/xres_buf.sdf", uut.rstb_level) ;
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$sdf_annotate("../../../caravel/sdf/user_id_programming.sdf", uut.user_id_value) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[0] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_1[1] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[0] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[1] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_bidir_2[2] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[0] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[1] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[2] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[3] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[4] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[5] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[6] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[7] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[8] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[9] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1[10] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[0] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[1] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[2] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[3] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[4] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_1a[5] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[0] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[1] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[2] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[3] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[4] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[5] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[6] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[7] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[8] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[9] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[10] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[11] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[12] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[13] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[14] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_control_block.sdf", uut.\gpio_control_in_2[15] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[0] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_0[1] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[0] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[1] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.\gpio_defaults_block_2[2] ) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_5) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_6) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_7) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_8) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_9) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_10) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_11) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_12) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_13) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_14) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_15) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_16) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_17) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_18) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_19) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_20) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_21) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_22) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_23) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_24) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_25) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_26) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_27) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_28) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_29) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_30) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_31) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_32) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_33) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_34) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_35) ;
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$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_36) ;
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||||
$sdf_annotate("../../../caravel/sdf/gpio_defaults_block.sdf", uut.gpio_defaults_block_37) ;
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||||
end
|
||||
`endif
|
||||
|
||||
// assign mprj_io[3] = 1'b1;
|
||||
|
||||
initial begin
|
||||
$dumpfile("la_test1.vcd");
|
||||
$dumpvars(0, la_test1_tb);
|
||||
|
||||
// Repeat cycles of 1000 clock edges as needed to complete testbench
|
||||
repeat (250) begin
|
||||
repeat (1000) @(posedge clock);
|
||||
// $display("+1000 cycles");
|
||||
end
|
||||
$display("%c[1;31m",27);
|
||||
`ifdef GL
|
||||
$display ("Monitor: Timeout, Test LA (GL) Failed");
|
||||
`else
|
||||
$display ("Monitor: Timeout, Test LA (RTL) Failed");
|
||||
`endif
|
||||
$display("%c[0m",27);
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial begin
|
||||
wait(checkbits == 16'hAB40);
|
||||
$display("LA Test 1 started");
|
||||
wait(checkbits == 16'hAB41);
|
||||
wait(checkbits == 16'hAB51);
|
||||
$display("LA Test 2 passed");
|
||||
#10000;
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial begin
|
||||
RSTB <= 1'b0;
|
||||
CSB <= 1'b1; // Force CSB high
|
||||
#2000;
|
||||
RSTB <= 1'b1; // Release reset
|
||||
#170000;
|
||||
CSB = 1'b0; // CSB can be released
|
||||
end
|
||||
|
||||
initial begin // Power-up sequence
|
||||
power1 <= 1'b0;
|
||||
power2 <= 1'b0;
|
||||
#200;
|
||||
power1 <= 1'b1;
|
||||
#200;
|
||||
power2 <= 1'b1;
|
||||
end
|
||||
|
||||
wire flash_csb;
|
||||
wire flash_clk;
|
||||
wire flash_io0;
|
||||
wire flash_io1;
|
||||
|
||||
wire VDD1V8;
|
||||
wire VDD3V3;
|
||||
wire VSS;
|
||||
|
||||
assign VDD3V3 = power1;
|
||||
assign VDD1V8 = power2;
|
||||
assign VSS = 1'b0;
|
||||
|
||||
assign mprj_io[3] = 1; // Force CSB high.
|
||||
assign mprj_io[0] = 0; // Disable debug mode
|
||||
|
||||
caravel uut (
|
||||
.vddio (VDD3V3),
|
||||
.vddio_2 (VDD3V3),
|
||||
.vssio (VSS),
|
||||
.vssio_2 (VSS),
|
||||
.vdda (VDD3V3),
|
||||
.vssa (VSS),
|
||||
.vccd (VDD1V8),
|
||||
.vssd (VSS),
|
||||
.vdda1 (VDD3V3),
|
||||
.vdda1_2 (VDD3V3),
|
||||
.vdda2 (VDD3V3),
|
||||
.vssa1 (VSS),
|
||||
.vssa1_2 (VSS),
|
||||
.vssa2 (VSS),
|
||||
.vccd1 (VDD1V8),
|
||||
.vccd2 (VDD1V8),
|
||||
.vssd1 (VSS),
|
||||
.vssd2 (VSS),
|
||||
.clock (clock),
|
||||
.gpio (gpio),
|
||||
.mprj_io (mprj_io),
|
||||
.flash_csb(flash_csb),
|
||||
.flash_clk(flash_clk),
|
||||
.flash_io0(flash_io0),
|
||||
.flash_io1(flash_io1),
|
||||
.resetb (RSTB)
|
||||
);
|
||||
|
||||
spiflash #(
|
||||
.FILENAME("la_test1.hex")
|
||||
) spiflash (
|
||||
.csb(flash_csb),
|
||||
.clk(flash_clk),
|
||||
.io0(flash_io0),
|
||||
.io1(flash_io1),
|
||||
.io2(), // not used
|
||||
.io3() // not used
|
||||
);
|
||||
|
||||
// Testbench UART
|
||||
tbuart tbuart (
|
||||
.ser_rx(uart_tx)
|
||||
);
|
||||
|
||||
endmodule
|
||||
`default_nettype wire
|
||||
Reference in New Issue
Block a user