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Corey Hahn
2026-02-23 20:42:11 -07:00
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66
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
`ifndef __GLOBAL_DEFINE_H
// Global parameters
`define __GLOBAL_DEFINE_H
`define MPRJ_IO_PADS_1 19 /* number of user GPIO pads on user1 side */
`define MPRJ_IO_PADS_2 19 /* number of user GPIO pads on user2 side */
`define MPRJ_IO_PADS (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)
`define MPRJ_PWR_PADS_1 2 /* vdda1, vccd1 enable/disable control */
`define MPRJ_PWR_PADS_2 2 /* vdda2, vccd2 enable/disable control */
`define MPRJ_PWR_PADS (`MPRJ_PWR_PADS_1 + `MPRJ_PWR_PADS_2)
// Analog pads are only used by the "caravan" module and associated
// modules such as user_analog_project_wrapper and chip_io_alt.
`define ANALOG_PADS_1 5
`define ANALOG_PADS_2 6
`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)
// Size of soc_mem_synth
// Type and size of soc_mem
// `define USE_OPENRAM
`define USE_CUSTOM_DFFRAM
// don't change the following without double checking addr widths
`define MEM_WORDS 256
// Number of columns in the custom memory; takes one of three values:
// 1 column : 1 KB, 2 column: 2 KB, 4 column: 4KB
`define DFFRAM_WSIZE 4
`define DFFRAM_USE_LATCH 0
// not really parameterized but just to easily keep track of the number
// of ram_block across different modules
`define RAM_BLOCKS 1
// Clock divisor default value
`define CLK_DIV 3'b010
// GPIO control default mode and enable for most I/Os
// Most I/Os set to be user input pins on startup.
// NOTE: To be modified, with GPIOs 5 to 35 being set from a build-time-
// programmable block.
`define MGMT_INIT 1'b0
`define OENB_INIT 1'b0
`define DM_INIT 3'b001
`endif // __GLOBAL_DEFINE_H

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verilog/rtl/uprj_netlists.v Normal file
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// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
// Include caravel global defines for the number of the user project IO pads
`include "defines.v"
`define USE_POWER_PINS
`ifdef GL
// Assume default net type to be wire because GL netlists don't have the wire definitions
`default_nettype wire
`include "gl/user_project_wrapper.v"
`include "gl/user_proj_example.v"
`else
`include "user_project_wrapper.v"
`include "user_proj_example.v"
`endif

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verilog/rtl/user_defines.v Normal file
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// SPDX-FileCopyrightText: 2022 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
`ifndef __USER_DEFINES_H
// User GPIO initial configuration parameters
`define __USER_DEFINES_H
// deliberately erroneous placeholder value; user required to config GPIO's to other
`define GPIO_MODE_INVALID 13'hXXXX
// Authoritive source of these MODE defs is: caravel/verilog/rtl/user_defines.v
// Useful GPIO mode values. These match the names used in defs.h.
//
`define GPIO_MODE_MGMT_STD_INPUT_NOPULL 13'h0403
`define GPIO_MODE_MGMT_STD_INPUT_PULLDOWN 13'h0c01
`define GPIO_MODE_MGMT_STD_INPUT_PULLUP 13'h0801
`define GPIO_MODE_MGMT_STD_OUTPUT 13'h1809
`define GPIO_MODE_MGMT_STD_BIDIRECTIONAL 13'h1801
`define GPIO_MODE_MGMT_STD_ANALOG 13'h000b
`define GPIO_MODE_USER_STD_INPUT_NOPULL 13'h0402
`define GPIO_MODE_USER_STD_INPUT_PULLDOWN 13'h0c00
`define GPIO_MODE_USER_STD_INPUT_PULLUP 13'h0800
`define GPIO_MODE_USER_STD_OUTPUT 13'h1808
`define GPIO_MODE_USER_STD_BIDIRECTIONAL 13'h1800
`define GPIO_MODE_USER_STD_OUT_MONITORED 13'h1802
`define GPIO_MODE_USER_STD_ANALOG 13'h000a
// The power-on configuration for GPIO 0 to 4 is fixed and cannot be
// modified (allowing the SPI and debug to always be accessible unless
// overridden by a flash program).
// The values below can be any of the standard types defined above,
// or they can be any 13-bit value if the user wants a non-standard
// startup state for the GPIO. By default, every GPIO from 5 to 37
// is set to power up as an input controlled by the management SoC.
// Users may want to redefine these so that the user project powers
// up in a state that can be used immediately without depending on
// the management SoC to run a startup program to configure the GPIOs.
`define USER_CONFIG_GPIO_5_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_6_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_7_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_8_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_9_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_10_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_11_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_12_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_13_INIT `GPIO_MODE_INVALID
// Configurations of GPIO 14 to 24 are used on caravel but not caravan.
`define USER_CONFIG_GPIO_14_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_15_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_16_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_17_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_18_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_19_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_20_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_21_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_22_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_23_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_24_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_25_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_26_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_27_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_28_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_29_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_30_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_31_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_32_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_33_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_34_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_35_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_36_INIT `GPIO_MODE_INVALID
`define USER_CONFIG_GPIO_37_INIT `GPIO_MODE_INVALID
`endif // __USER_DEFINES_H

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// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_proj_example
*
* This is an example of a (trivially simple) user project,
* showing how the user project can connect to the logic
* analyzer, the wishbone bus, and the I/O pads.
*
* This project generates an integer count, which is output
* on the user area GPIO pads (digital output only). The
* wishbone connection allows the project to be controlled
* (start and stop) from the management SoC program.
*
* See the testbenches in directory "mprj_counter" for the
* example programs that drive this user project. The three
* testbenches are "io_ports", "la_test1", and "la_test2".
*
*-------------------------------------------------------------
*/
module user_proj_example #(
parameter BITS = 16
)(
`ifdef USE_POWER_PINS
inout vccd1, // User area 1 1.8V supply
inout vssd1, // User area 1 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [BITS-1:0] io_in,
output [BITS-1:0] io_out,
output [BITS-1:0] io_oeb,
// IRQ
output [2:0] irq
);
wire clk;
wire rst;
wire [BITS-1:0] rdata;
wire [BITS-1:0] wdata;
wire [BITS-1:0] count;
wire valid;
wire [3:0] wstrb;
wire [BITS-1:0] la_write;
// WB MI A
assign valid = wbs_cyc_i && wbs_stb_i;
assign wstrb = wbs_sel_i & {4{wbs_we_i}};
assign wbs_dat_o = {{(32-BITS){1'b0}}, rdata};
assign wdata = wbs_dat_i[BITS-1:0];
// IO
assign io_out = count;
assign io_oeb = {(BITS){rst}};
// IRQ
assign irq = 3'b000; // Unused
// LA
assign la_data_out = {{(128-BITS){1'b0}}, count};
// Assuming LA probes [63:32] are for controlling the count register
assign la_write = ~la_oenb[63:64-BITS] & ~{BITS{valid}};
// Assuming LA probes [65:64] are for controlling the count clk & reset
assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
counter #(
.BITS(BITS)
) counter(
.clk(clk),
.reset(rst),
.ready(wbs_ack_o),
.valid(valid),
.rdata(rdata),
.wdata(wbs_dat_i[BITS-1:0]),
.wstrb(wstrb),
.la_write(la_write),
.la_input(la_data_in[63:64-BITS]),
.count(count)
);
endmodule
module counter #(
parameter BITS = 16
)(
input clk,
input reset,
input valid,
input [3:0] wstrb,
input [BITS-1:0] wdata,
input [BITS-1:0] la_write,
input [BITS-1:0] la_input,
output reg ready,
output reg [BITS-1:0] rdata,
output reg [BITS-1:0] count
);
always @(posedge clk) begin
if (reset) begin
count <= 1'b0;
ready <= 1'b0;
end else begin
ready <= 1'b0;
if (~|la_write) begin
count <= count + 1'b1;
end
if (valid && !ready) begin
ready <= 1'b1;
rdata <= count;
if (wstrb[0]) count[7:0] <= wdata[7:0];
if (wstrb[1]) count[15:8] <= wdata[15:8];
end else if (|la_write) begin
count <= la_write & la_input;
end
end
end
endmodule
`default_nettype wire

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// SPDX-FileCopyrightText: 2020 Efabless Corporation
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
// SPDX-License-Identifier: Apache-2.0
`default_nettype none
/*
*-------------------------------------------------------------
*
* user_project_wrapper
*
* This wrapper enumerates all of the pins available to the
* user for the user project.
*
* An example user project is provided in this wrapper. The
* example should be removed and replaced with the actual
* user project.
*
*-------------------------------------------------------------
*/
module user_project_wrapper #(
parameter BITS = 32
) (
`ifdef USE_POWER_PINS
inout vdda1, // User area 1 3.3V supply
inout vdda2, // User area 2 3.3V supply
inout vssa1, // User area 1 analog ground
inout vssa2, // User area 2 analog ground
inout vccd1, // User area 1 1.8V supply
inout vccd2, // User area 2 1.8v supply
inout vssd1, // User area 1 digital ground
inout vssd2, // User area 2 digital ground
`endif
// Wishbone Slave ports (WB MI A)
input wb_clk_i,
input wb_rst_i,
input wbs_stb_i,
input wbs_cyc_i,
input wbs_we_i,
input [3:0] wbs_sel_i,
input [31:0] wbs_dat_i,
input [31:0] wbs_adr_i,
output wbs_ack_o,
output [31:0] wbs_dat_o,
// Logic Analyzer Signals
input [127:0] la_data_in,
output [127:0] la_data_out,
input [127:0] la_oenb,
// IOs
input [`MPRJ_IO_PADS-1:0] io_in,
output [`MPRJ_IO_PADS-1:0] io_out,
output [`MPRJ_IO_PADS-1:0] io_oeb,
// Analog (direct connection to GPIO pad---use with caution)
// Note that analog I/O is not available on the 7 lowest-numbered
// GPIO pads, and so the analog_io indexing is offset from the
// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
inout [`MPRJ_IO_PADS-10:0] analog_io,
// Independent clock (on independent integer divider)
input user_clock2,
// User maskable interrupt signals
output [2:0] user_irq
);
/*--------------------------------------*/
/* User project is instantiated here */
/*--------------------------------------*/
user_proj_example mprj (
`ifdef USE_POWER_PINS
.vccd1(vccd1), // User area 1 1.8V power
.vssd1(vssd1), // User area 1 digital ground
`endif
.wb_clk_i(wb_clk_i),
.wb_rst_i(wb_rst_i),
// MGMT SoC Wishbone Slave
.wbs_cyc_i(wbs_cyc_i),
.wbs_stb_i(wbs_stb_i),
.wbs_we_i(wbs_we_i),
.wbs_sel_i(wbs_sel_i),
.wbs_adr_i(wbs_adr_i),
.wbs_dat_i(wbs_dat_i),
.wbs_ack_o(wbs_ack_o),
.wbs_dat_o(wbs_dat_o),
// Logic Analyzer
.la_data_in(la_data_in),
.la_data_out(la_data_out),
.la_oenb (la_oenb),
// IO Pads
.io_in ({io_in[37:30],io_in[7:0]}),
.io_out({io_out[37:30],io_out[7:0]}),
.io_oeb({io_oeb[37:30],io_oeb[7:0]}),
// IRQ
.irq(user_irq)
);
endmodule // user_project_wrapper
`default_nettype wire