Initial commit

.cf/repo.json

@@ -0,0 +1,8 @@
+{
+  "version": "v1",
+  "changes": [
+    "README.md",
+    "Makefile",
+    "openlane/Makefile"
+  ]
+}

.github/scripts/get_designs.py

@@ -0,0 +1,29 @@
+import argparse
+import json
+
+
+def parse_lvs_config(file_path):
+    """Parses the LVS config file at the specified path."""
+    with open(file_path) as f:
+        data = json.load(f)
+    return data['LVS_VERILOG_FILES']
+
+
+def main():
+    parser = argparse.ArgumentParser()
+    parser.add_argument("--design", help="The path to the design.")
+    args = parser.parse_args()
+
+    config_file = f"{args.design}/lvs/user_project_wrapper/lvs_config.json"
+    data = parse_lvs_config(config_file)
+    f = open("harden_sequence.txt", "w")
+    for d in data:
+        macro_name = d.split('/')[-1].split('.v')[0]
+        if macro_name.startswith('$'):
+            macro_name = 'user_project_wrapper'
+        f.write(f"{macro_name} ")
+    f.close()
+
+
+if __name__ == "__main__":
+    main()

.github/workflows/user_project_ci.yml

@@ -0,0 +1,236 @@
+name: CI
+
+on:
+  push:
+  pull_request:
+  workflow_dispatch:
+
+jobs:
+  hardening:
+    timeout-minutes: 720
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        pdk: ["sky130A", "sky130B"]
+    steps:
+      - uses: actions/checkout@v4
+
+      - name: Set up QEMU
+        uses: docker/setup-qemu-action@v1
+
+      - name: Set up Docker Buildx
+        uses: docker/setup-buildx-action@v1
+
+      - name: Install ChipFoundry CLI
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y python3 python3-pip python3-venv python3-tk
+          pip3 install chipfoundry-cli
+
+      - name: Initialize Project
+        run: |
+          mkdir -p .cf
+          python3 <<EOF
+          import json
+          import os
+          from pathlib import Path
+          
+          project_name = os.path.basename(os.getcwd())
+          project_json = Path('.cf/project.json')
+          
+          data = {
+              "project": {
+                  "name": project_name,
+                  "type": "digital",
+                  "user": "chipfoundry",
+                  "version": "1.0.0",
+                  "user_project_wrapper_hash": "",
+                  "submission_state": "Draft"
+              }
+          }
+          
+          with open(project_json, 'w') as f:
+              json.dump(data, f, indent=2)
+          EOF
+
+      - name: Setup Dependencies
+        run: |
+          cf setup --pdk ${{ matrix.pdk }} --only-openlane --only-pdk
+
+      - name: Harden Designs
+        run: |
+          set -e
+          python3 .github/scripts/get_designs.py --design ${{ github.workspace }}
+          for design in $(cat harden_sequence.txt); do
+            cf harden $design || exit 1
+          done
+
+      - name: Upload Hardened Design
+        uses: actions/upload-artifact@v4
+        with:
+          name: design-${{ matrix.pdk }}
+          path: |
+            ${{ github.workspace }}/gds
+            ${{ github.workspace }}/signoff
+            ${{ github.workspace }}/.cf/project.json
+          retention-days: 1
+
+  rtl-verification:
+    timeout-minutes: 720
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        pdk: ["sky130A", "sky130B"]
+    steps:
+      - uses: actions/checkout@v4
+
+      - name: Set up QEMU
+        uses: docker/setup-qemu-action@v1
+
+      - name: Set up Docker Buildx
+        uses: docker/setup-buildx-action@v1
+
+      - name: Install ChipFoundry CLI
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y python3 python3-pip python3-venv
+          pip3 install chipfoundry-cli
+
+      - name: Initialize Project
+        run: |
+          mkdir -p .cf
+          python3 <<EOF
+          import json
+          import os
+          from pathlib import Path
+          
+          project_name = os.path.basename(os.getcwd())
+          project_json = Path('.cf/project.json')
+          
+          data = {
+              "project": {
+                  "name": project_name,
+                  "type": "digital",
+                  "user": "chipfoundry",
+                  "version": "1.0.0",
+                  "user_project_wrapper_hash": "",
+                  "submission_state": "Draft"
+              }
+          }
+          
+          with open(project_json, 'w') as f:
+              json.dump(data, f, indent=2)
+          EOF
+
+      - name: Setup Dependencies
+        run: |
+          cf setup --pdk ${{ matrix.pdk }} --only-caravel --only-mcw --only-pdk --only-cocotb
+
+      - name: Configure GPIO (non-interactive)
+        run: |
+          python3 <<EOF
+          import json
+          from pathlib import Path
+          
+          project_json = Path('.cf/project.json')
+          with open(project_json) as f:
+              data = json.load(f)
+          
+          # Set default GPIO config (all as user input no pull)
+          gpio_config = {}
+          for gpio in range(5, 38):
+              gpio_config[str(gpio)] = "13'h0402"  # GPIO_MODE_USER_STD_INPUT_NOPULL
+          
+          data['project']['gpio_config'] = gpio_config
+          
+          with open(project_json, 'w') as f:
+              json.dump(data, f, indent=2)
+          EOF
+
+      - name: Run RTL Verification
+        run: |
+          cf verify --all
+
+  precheck:
+    timeout-minutes: 720
+    runs-on: ubuntu-latest
+    strategy:
+      matrix:
+        pdk: ["sky130A", "sky130B"]
+    needs: [hardening]
+    steps:
+      - uses: actions/checkout@v4
+
+      - name: Set up QEMU
+        uses: docker/setup-qemu-action@v1
+
+      - name: Set up Docker Buildx
+        uses: docker/setup-buildx-action@v1
+
+      - name: Install ChipFoundry CLI
+        run: |
+          sudo apt-get update
+          sudo apt-get install -y python3 python3-pip
+          pip3 install chipfoundry-cli
+
+      - name: Initialize Project
+        run: |
+          mkdir -p .cf
+          python3 <<EOF
+          import json
+          import os
+          from pathlib import Path
+          
+          project_name = os.path.basename(os.getcwd())
+          project_json = Path('.cf/project.json')
+          
+          data = {
+              "pdk": "${{ matrix.pdk }}",
+              "project": {
+                  "name": project_name,
+                  "type": "digital",
+                  "user": "chipfoundry",
+                  "version": "1.0.0",
+                  "user_project_wrapper_hash": "",
+                  "submission_state": "Draft"
+              }
+          }
+          
+          with open(project_json, 'w') as f:
+              json.dump(data, f, indent=2)
+          EOF
+
+      - name: Setup Dependencies
+        run: |
+          cf setup --pdk ${{ matrix.pdk }} --only-pdk --only-precheck
+
+      - name: Download Hardened Design
+        uses: actions/download-artifact@v4
+        with:
+          name: design-${{ matrix.pdk }}
+          path: ${{ github.workspace }}
+
+      - name: Configure GPIO (non-interactive)
+        run: |
+          python3 <<EOF
+          import json
+          from pathlib import Path
+          
+          project_json = Path('.cf/project.json')
+          with open(project_json) as f:
+              data = json.load(f)
+          
+          # Set default GPIO config (all as user input no pull)
+          gpio_config = {}
+          for gpio in range(5, 38):
+              gpio_config[str(gpio)] = "13'h0402"  # GPIO_MODE_USER_STD_INPUT_NOPULL
+          
+          data['project']['gpio_config'] = gpio_config
+          
+          with open(project_json, 'w') as f:
+              json.dump(data, f, indent=2)
+          EOF
+
+      - name: Run Precheck
+        run: |
+          cf precheck

.gitignore

@@ -0,0 +1,17 @@
+/.idea/
+/precheck_results/
+*/tmp
+*/*/tmp
+*.hex*
+*.lst
+*.vcd
+*.gtkw
+/env
+/venv
+/venv-cocotb
+/caravel
+/dependencies
+/mgmt_core_wrapper
+/logs
+openlane2-venv
+design_info.yaml

.readthedocs.yaml

@@ -0,0 +1,22 @@
+# .readthedocs.yaml
+# Read the Docs configuration file
+# See https://docs.readthedocs.io/en/stable/config-file/v2.html for details
+
+# Required
+version: 2
+
+# Set the version of Python and other tools you might need
+build:
+  os: ubuntu-22.04
+  tools:
+    python: "3.10"
+
+# Build documentation in the docs/ directory with Sphinx
+sphinx:
+  configuration: docs/source/conf.py
+
+# We recommend specifying your dependencies to enable reproducible builds:
+# https://docs.readthedocs.io/en/stable/guides/reproducible-builds.html
+python:
+  install:
+  - requirements: docs/requirements.txt

LICENSE

@@ -0,0 +1,201 @@
+                                 Apache License
+                           Version 2.0, January 2004
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+
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Makefile

@@ -0,0 +1,450 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+export CUP_ROOT ?= $(shell pwd)
+export TIMING_ROOT ?= $(shell pwd)/dependencies/timing-scripts
+export PROJECT_ROOT = $(CUP_ROOT)
+MAKEFLAGS += --warn-undefined-variables
+
+export CARAVEL_ROOT?=$(PWD)/caravel
+export UPRJ_ROOT?=$(PWD)
+PRECHECK_ROOT?=${HOME}/mpw_precheck
+export MCW_ROOT?=$(PWD)/mgmt_core_wrapper
+SIM?=RTL
+
+# Install lite version of caravel, (1): caravel-lite, (0): caravel
+CARAVEL_LITE?=1
+
+# PDK switch varient
+export PDK?=sky130A
+#export PDK?=gf180mcuC
+export PDKPATH?=$(PDK_ROOT)/$(PDK)
+
+PYTHON_BIN ?= python3
+
+ROOTLESS ?= 0
+USER_ARGS = -u $$(id -u $$USER):$$(id -g $$USER)
+ifeq ($(ROOTLESS), 1)
+	USER_ARGS =
+endif
+export OPENLANE_ROOT?=$(PWD)/dependencies/openlane_src
+export PDK_ROOT?=$(PWD)/dependencies/pdks
+export DISABLE_LVS?=0
+
+export ROOTLESS
+
+export CIEL_DATA_SOURCE=static-web:https://chipfoundry.github.io/ciel-releases
+
+ifeq ($(PDK),sky130A)
+export OPEN_PDKS_COMMIT_LVS?=6d4d11780c40b20ee63cc98e645307a9bf2b2ab8
+export OPEN_PDKS_COMMIT?=3e0e31dcce8519a7dbb82590346db16d91b7244f
+MPW_TAG ?= CC2509
+ifeq ($(CARAVEL_LITE),1)
+CARAVEL_NAME := caravel-lite
+CARAVEL_REPO := https://github.com/chipfoundry/caravel-lite
+CARAVEL_TAG := $(MPW_TAG)
+else
+CARAVEL_NAME := caravel
+CARAVEL_REPO := https://github.com/chipfoundry/caravel
+CARAVEL_TAG := $(MPW_TAG)
+endif
+endif
+
+ifeq ($(PDK),sky130B)
+export OPEN_PDKS_COMMIT_LVS?=6d4d11780c40b20ee63cc98e645307a9bf2b2ab8
+export OPEN_PDKS_COMMIT?=3e0e31dcce8519a7dbb82590346db16d91b7244f
+MPW_TAG ?= 2024.09.12-1
+ifeq ($(CARAVEL_LITE),1)
+CARAVEL_NAME := caravel-lite
+CARAVEL_REPO := https://github.com/chipfoundry/caravel-lite
+CARAVEL_TAG := $(MPW_TAG)
+else
+CARAVEL_NAME := caravel
+CARAVEL_REPO := https://github.com/chipfoundry/caravel
+CARAVEL_TAG := $(MPW_TAG)
+endif
+endif
+
+ifeq ($(PDK),gf180mcuD)
+MPW_TAG ?= gfmpw-1c
+CARAVEL_NAME := caravel
+CARAVEL_REPO := https://github.com/chipfoundry/caravel-gf180mcu
+CARAVEL_TAG := $(MPW_TAG)
+export OPEN_PDKS_COMMIT?=78b7bc32ddb4b6f14f76883c2e2dc5b5de9d1cbc
+endif
+
+# Include Caravel Makefile Targets
+.PHONY: % : check-caravel
+%:
+	export CARAVEL_ROOT=$(CARAVEL_ROOT) && export MPW_TAG=$(MPW_TAG) && $(MAKE) -f $(CARAVEL_ROOT)/Makefile $@
+
+.PHONY: check-deprecated
+check-deprecated:
+	@if [ "$$DISABLE_DEPRECATED_MAKEFILE_PROMPT" = "1" ]; then \
+		exit 0; \
+	fi; \
+	if ! [ -t 0 ]; then \
+		printf "ERROR: This Makefile target is deprecated and requires confirmation.\n"; \
+		printf "Use the cf CLI instead, or set DISABLE_DEPRECATED_MAKEFILE_PROMPT=1 to bypass.\n"; \
+		exit 1; \
+	fi; \
+	printf "\033[33mWARNING: Deprecated Makefile target.\033[0m\n"; \
+	printf "\033[33mInstall the cf CLI:\033[0m\n"; \
+	printf "  pip install cf-cli\n"; \
+	printf "\033[33mContinue? [y/N]: \033[0m"; \
+	read -r reply; \
+	case "$$reply" in \
+		Y|y|yes|YES) ;; \
+		*) echo "Aborted."; exit 1;; \
+	esac
+
+.PHONY: check-deprecated install
+install:
+	if [ -d "$(CARAVEL_ROOT)" ]; then\
+		echo "Deleting exisiting $(CARAVEL_ROOT)" && \
+		rm -rf $(CARAVEL_ROOT) && sleep 2;\
+	fi
+	echo "Installing $(CARAVEL_NAME).."
+	git clone -b $(CARAVEL_TAG) $(CARAVEL_REPO) $(CARAVEL_ROOT) --depth=1
+
+# Install DV setup
+.PHONY: simenv
+simenv:
+	docker pull chipfoundry/dv:latest
+
+# Install cocotb docker
+.PHONY: simenv-cocotb
+simenv-cocotb:
+	docker pull chipfoundry/dv:cocotb
+
+.PHONY: setup
+setup: check-deprecated check_dependencies install check-env install_mcw openlane pdk-with-ciel setup-timing-scripts setup-cocotb precheck
+
+# Openlane
+
+dv_patterns=$(shell cd verilog/dv && find * -maxdepth 0 -type d)
+cocotb-dv_patterns=$(shell cd verilog/dv/cocotb && find . -name "*.c"  | sed -e 's|^.*/||' -e 's/.c//')
+dv-targets-rtl=$(dv_patterns:%=verify-%-rtl)
+cocotb-dv-targets-rtl=$(cocotb-dv_patterns:%=cocotb-verify-%-rtl)
+dv-targets-gl=$(dv_patterns:%=verify-%-gl)
+cocotb-dv-targets-gl=$(cocotb-dv_patterns:%=cocotb-verify-%-gl)
+dv-targets-gl-sdf=$(dv_patterns:%=verify-%-gl-sdf)
+
+TARGET_PATH=$(shell pwd)
+verify_command="source ~/.bashrc && cd ${TARGET_PATH}/verilog/dv/$* && export SIM=${SIM} && make"
+dv_base_dependencies=simenv
+docker_run_verify=\
+	docker run \
+		$(USER_ARGS) \
+		-v ${TARGET_PATH}:${TARGET_PATH} -v ${PDK_ROOT}:${PDK_ROOT} \
+		-v ${CARAVEL_ROOT}:${CARAVEL_ROOT} \
+		-v ${MCW_ROOT}:${MCW_ROOT} \
+		-e TARGET_PATH=${TARGET_PATH} -e PDK_ROOT=${PDK_ROOT} \
+		-e CARAVEL_ROOT=${CARAVEL_ROOT} \
+		-e TOOLS=/foss/tools/riscv-gnu-toolchain-rv32i/217e7f3debe424d61374d31e33a091a630535937 \
+		-e DESIGNS=$(TARGET_PATH) \
+		-e USER_PROJECT_VERILOG=$(TARGET_PATH)/verilog \
+		-e PDK=$(PDK) \
+		-e CORE_VERILOG_PATH=$(TARGET_PATH)/mgmt_core_wrapper/verilog \
+		-e CARAVEL_VERILOG_PATH=$(TARGET_PATH)/caravel/verilog \
+		-e MCW_ROOT=$(MCW_ROOT) \
+		chipfoundry/dv:latest \
+		sh -c $(verify_command)
+
+.PHONY: verify
+verify: $(dv-targets-rtl)
+
+.PHONY: verify-all-rtl
+verify-all-rtl: $(dv-targets-rtl)
+
+.PHONY: verify-all-gl
+verify-all-gl: $(dv-targets-gl)
+
+.PHONY: verify-all-gl-sdf
+verify-all-gl-sdf: $(dv-targets-gl-sdf)
+
+$(dv-targets-rtl): SIM=RTL
+$(dv-targets-rtl): verify-%-rtl: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+$(dv-targets-gl): SIM=GL
+$(dv-targets-gl): verify-%-gl: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+$(dv-targets-gl-sdf): SIM=GL_SDF
+$(dv-targets-gl-sdf): verify-%-gl-sdf: $(dv_base_dependencies)
+	$(docker_run_verify)
+
+make_what=setup $(blocks) $(dv-targets-rtl) $(dv-targets-gl) $(dv-targets-gl-sdf) $(clean-targets)
+.PHONY: what
+what:
+	# $(make_what)
+
+# Install LibreLane
+.PHONY: check-deprecated librelane openlane librelane-% openlane2-venv openlane2-docker-container
+openlane: librelane
+librelane: librelane-venv
+openlane2-venv: librelane-venv
+openlane2-docker-container: librelane-docker-image
+librelane-%:
+	$(MAKE) -C openlane $@
+	
+# Alias to install with Ciel
+pdk-with-volare:
+	$(MAKE) pdk-with-ciel
+
+#### Not sure if the targets following are of any use
+
+# Create symbolic links to caravel's main files
+.PHONY: simlink
+simlink: check-caravel
+### Symbolic links relative path to $CARAVEL_ROOT
+	$(eval MAKEFILE_PATH := $(shell realpath --relative-to=openlane $(CARAVEL_ROOT)/openlane/Makefile))
+	$(eval PIN_CFG_PATH  := $(shell realpath --relative-to=openlane/user_project_wrapper $(CARAVEL_ROOT)/openlane/user_project_wrapper_empty/pin_order.cfg))
+	mkdir -p openlane
+	mkdir -p openlane/user_project_wrapper
+	cd openlane &&\
+	ln -sf $(MAKEFILE_PATH) Makefile
+	cd openlane/user_project_wrapper &&\
+	ln -sf $(PIN_CFG_PATH) pin_order.cfg
+
+# Update Caravel
+.PHONY: update_caravel
+update_caravel: check-caravel
+	cd $(CARAVEL_ROOT)/ && git checkout $(CARAVEL_TAG) && git pull
+
+# Uninstall Caravel
+.PHONY: uninstall
+uninstall:
+	rm -rf $(CARAVEL_ROOT)
+
+
+# Install Pre-check
+# Default installs to the user home directory, override by "export PRECHECK_ROOT=<precheck-installation-path>"
+.PHONY: precheck
+precheck: check-deprecated
+	if [ -d "$(PRECHECK_ROOT)" ]; then\
+		echo "Deleting exisiting $(PRECHECK_ROOT)" && \
+		rm -rf $(PRECHECK_ROOT) && sleep 2;\
+	fi
+	@echo "Installing Precheck.."
+	@git clone --depth=1 https://github.com/chipfoundry/mpw_precheck.git $(PRECHECK_ROOT)
+	@docker pull chipfoundry/mpw_precheck:latest
+
+.PHONY: run-precheck
+run-precheck: check-deprecated check-pdk check-precheck
+	@if [ "$$DISABLE_LVS" = "1" ]; then\
+		$(eval INPUT_DIRECTORY := $(shell pwd)) \
+		cd $(PRECHECK_ROOT) && \
+		docker run -it -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+		-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(HOME)/.ipm:$(HOME)/.ipm \
+		-e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+		-e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e PDKPATH=$(PDKPATH) \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		chipfoundry/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK) license makefile default documentation consistency gpio_defines xor magic_drc klayout_feol klayout_beol klayout_offgrid klayout_met_min_ca_density klayout_pin_label_purposes_overlapping_drawing klayout_zeroarea"; \
+	else \
+		$(eval INPUT_DIRECTORY := $(shell pwd)) \
+		cd $(PRECHECK_ROOT) && \
+		docker run -it -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+		-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(HOME)/.ipm:$(HOME)/.ipm \
+		-e INPUT_DIRECTORY=$(INPUT_DIRECTORY) \
+		-e PDK_PATH=$(PDK_ROOT)/$(PDK) \
+		-e PDK_ROOT=$(PDK_ROOT) \
+		-e PDKPATH=$(PDKPATH) \
+		-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+		chipfoundry/mpw_precheck:latest bash -c "cd $(PRECHECK_ROOT) ; python3 mpw_precheck.py --input_directory $(INPUT_DIRECTORY) --pdk_path $(PDK_ROOT)/$(PDK)"; \
+	fi
+
+.PHONY: enable-lvs-pdk
+enable-lvs-pdk:
+	$(UPRJ_ROOT)/venv/bin/ciel enable $(OPEN_PDKS_COMMIT_LVS)
+
+BLOCKS = $(shell cd lvs && find * -maxdepth 0 -type d)
+LVS_BLOCKS = $(foreach block, $(BLOCKS), lvs-$(block))
+$(LVS_BLOCKS): lvs-% : ./lvs/%/lvs_config.json check-pdk check-precheck
+	@$(eval INPUT_DIRECTORY := $(shell pwd))
+	@cd $(PRECHECK_ROOT) && \
+	docker run -v $(PRECHECK_ROOT):$(PRECHECK_ROOT) \
+	-v $(INPUT_DIRECTORY):$(INPUT_DIRECTORY) \
+	-v $(PDK_ROOT):$(PDK_ROOT) \
+	-u $(shell id -u $(USER)):$(shell id -g $(USER)) \
+	chipfoundry/mpw_precheck:latest bash -c "export PYTHONPATH=$(PRECHECK_ROOT) ; cd $(PRECHECK_ROOT) ; python3 checks/lvs_check/lvs.py --pdk_path $(PDK_ROOT)/$(PDK) --design_directory $(INPUT_DIRECTORY) --output_directory $(INPUT_DIRECTORY)/lvs --design_name $* --config_file $(INPUT_DIRECTORY)/lvs/$*/lvs_config.json"
+
+.PHONY: clean
+clean:
+	cd ./verilog/dv/ && \
+		$(MAKE) -j$(THREADS) clean
+
+check-caravel:
+	@if [ ! -d "$(CARAVEL_ROOT)" ]; then \
+		echo "Caravel Root: "$(CARAVEL_ROOT)" doesn't exists, please export the correct path before running make. "; \
+		exit 1; \
+	fi
+
+check-precheck:
+	@if [ ! -d "$(PRECHECK_ROOT)" ]; then \
+		echo "Pre-check Root: "$(PRECHECK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+		exit 1; \
+	fi
+
+check-pdk:
+	@if [ ! -d "$(PDK_ROOT)" ]; then \
+		echo "PDK Root: "$(PDK_ROOT)" doesn't exists, please export the correct path before running make. "; \
+		exit 1; \
+	fi
+
+.PHONY: help
+help:
+	cd $(CARAVEL_ROOT) && $(MAKE) help
+	@$(MAKE) -pRrq -f $(lastword $(MAKEFILE_LIST)) : 2>/dev/null | awk -v RS= -F: '/^# File/,/^# Finished Make data base/ {if ($$1 !~ "^[#.]") {print $$1}}' | sort | egrep -v -e '^[^[:alnum:]]' -e '^$@$$'
+
+.PHONY: check_dependencies
+check_dependencies:
+	@if [ ! -d "$(PWD)/dependencies" ]; then \
+		mkdir $(PWD)/dependencies; \
+	fi
+
+timing-scripts-repo=https://github.com/chipfoundry/timing-scripts.git
+
+$(TIMING_ROOT):
+	@mkdir -p $(CUP_ROOT)/dependencies
+	@git clone $(timing-scripts-repo) $(TIMING_ROOT)
+
+.PHONY: setup-timing-scripts
+setup-timing-scripts: $(TIMING_ROOT)
+	@( cd $(TIMING_ROOT) && git pull )
+	@#( cd $(TIMING_ROOT) && git fetch && git checkout $(MPW_TAG); )
+
+.PHONY: install-caravel-cocotb
+install-caravel-cocotb:
+	rm -rf ./venv-cocotb
+	$(PYTHON_BIN) -m venv ./venv-cocotb
+	./venv-cocotb/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir pip
+	./venv-cocotb/bin/$(PYTHON_BIN) -m pip install --upgrade --no-cache-dir caravel-cocotb
+
+.PHONY: setup-cocotb-env
+setup-cocotb-env:
+	@(python3 $(PROJECT_ROOT)/verilog/dv/setup-cocotb.py $(CARAVEL_ROOT) $(MCW_ROOT) $(PDK_ROOT) $(PDK) $(PROJECT_ROOT))
+
+.PHONY: setup-cocotb
+setup-cocotb: install-caravel-cocotb setup-cocotb-env simenv-cocotb
+
+.PHONY: cocotb-verify-all-rtl
+cocotb-verify-all-rtl: check-deprecated
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && $(PROJECT_ROOT)/venv-cocotb/bin/caravel_cocotb -tl user_proj_tests/user_proj_tests.yaml )
+	
+.PHONY: cocotb-verify-all-gl
+cocotb-verify-all-gl: check-deprecated
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && $(PROJECT_ROOT)/venv-cocotb/bin/caravel_cocotb -tl user_proj_tests/user_proj_tests_gl.yaml -sim GL)
+
+$(cocotb-dv-targets-rtl): cocotb-verify-%-rtl: check-deprecated
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && $(PROJECT_ROOT)/venv-cocotb/bin/caravel_cocotb -t $*  )
+	
+$(cocotb-dv-targets-gl): cocotb-verify-%-gl: check-deprecated
+	@(cd $(PROJECT_ROOT)/verilog/dv/cocotb && $(PROJECT_ROOT)/venv-cocotb/bin/caravel_cocotb -t $* -sim GL)
+
+./verilog/gl/user_project_wrapper.v:
+	$(error you don't have $@)
+
+./env/spef-mapping.tcl:
+	@echo "run the following:"
+	@echo "make extract-parasitics"
+	@echo "make create-spef-mapping"
+	exit 1
+
+.PHONY: create-spef-mapping
+create-spef-mapping: ./verilog/gl/user_project_wrapper.v
+	docker run \
+		--rm \
+		$(USER_ARGS) \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(CUP_ROOT):$(CUP_ROOT) \
+		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-v $(MCW_ROOT):$(MCW_ROOT) \
+		-v $(TIMING_ROOT):$(TIMING_ROOT) \
+		-w $(shell pwd) \
+		chipfoundry/timing-scripts:latest \
+		python3 $(TIMING_ROOT)/scripts/generate_spef_mapping.py \
+			-i ./verilog/gl/user_project_wrapper.v \
+			-o ./env/spef-mapping.tcl \
+			--pdk-path $(PDK_ROOT)/$(PDK) \
+			--macro-parent chip_core/mprj \
+			--project-root "$(CUP_ROOT)"
+
+
+.PHONY: extract-parasitics
+extract-parasitics: ./verilog/gl/user_project_wrapper.v
+	docker run \
+		--rm \
+		$(USER_ARGS) \
+		-v $(PDK_ROOT):$(PDK_ROOT) \
+		-v $(CUP_ROOT):$(CUP_ROOT) \
+		-v $(CARAVEL_ROOT):$(CARAVEL_ROOT) \
+		-v $(MCW_ROOT):$(MCW_ROOT) \
+		-v $(TIMING_ROOT):$(TIMING_ROOT) \
+		-w $(shell pwd) \
+		chipfoundry/timing-scripts:latest \
+		python3 $(TIMING_ROOT)/scripts/get_macros.py \
+			-i ./verilog/gl/user_project_wrapper.v \
+			-o ./tmp-macros-list \
+			--project-root "$(CUP_ROOT)" \
+			--pdk-path $(PDK_ROOT)/$(PDK)
+	@cat ./tmp-macros-list | cut -d " " -f2 \
+		| xargs -I % bash -c "$(MAKE) -C $(TIMING_ROOT) \
+			-f $(TIMING_ROOT)/timing.mk rcx-% || echo 'Cannot extract %. Probably no def for this macro'"
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk rcx-user_project_wrapper
+	@cat ./tmp-macros-list
+	@rm ./tmp-macros-list
+
+.PHONY: caravel-sta
+caravel-sta: ./env/spef-mapping.tcl
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-typ -j3
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-fast -j3
+	@$(MAKE) -C $(TIMING_ROOT) -f $(TIMING_ROOT)/timing.mk caravel-timing-slow -j3
+	@echo =============================================Summary=============================================
+	@find $(PROJECT_ROOT)/signoff/caravel/openlane-signoff/timing/*/ -name "summary.log" | head -n1 \
+		| xargs head -n5 | tail -n1
+	@find $(PROJECT_ROOT)/signoff/caravel/openlane-signoff/timing/*/ -name "summary.log" \
+		| xargs -I {} bash -c "head -n7 {} | tail -n1"
+	@echo =================================================================================================
+	@echo "You can find results for all corners in $(CUP_ROOT)/signoff/caravel/openlane-signoff/timing/"
+	@echo "Check summary.log of a specific corner to point to reports with reg2reg violations"
+	@echo "Cap and slew violations are inside summary.log file itself"
+
+blocks=$(shell cd $(PROJECT_ROOT)/openlane && find * -maxdepth 0 -type d)
+.PHONY: $(blocks)
+$(blocks): % :
+	$(MAKE) -C openlane $*
+
+.PHONY: harden
+harden: check-deprecated $(blocks)
+
+clean-targets=$(blocks:%=clean-%)
+.PHONY: $(clean-targets)
+$(clean-targets): clean-% :
+	rm -f ./verilog/gl/$*.v
+	rm -f ./spef/$*.spef
+	rm -f ./sdc/$*.sdc
+	rm -f ./sdf/$*.sdf
+	rm -f ./gds/$*.gds
+	rm -f ./mag/$*.mag
+	rm -f ./lef/$*.lef
+	rm -f ./maglef/*.maglef

README.md

@@ -0,0 +1,231 @@
+<div align="center">
+
+<img src="https://umsousercontent.com/lib_lnlnuhLgkYnZdkSC/hj0vk05j0kemus1i.png" alt="ChipFoundry Logo" height="140" />
+
+[![Typing SVG](https://readme-typing-svg.demolab.com?font=Inter&size=44&duration=3000&pause=600&color=4C6EF5&center=true&vCenter=true&width=1100&lines=Caravel+User+Project+Template;OpenLane+%2B+ChipFoundry+Flow;Verification+and+Shuttle-Ready)](https://git.io/typing-svg)
+
+[![License](https://img.shields.io/badge/License-Apache%202.0-blue.svg)](https://opensource.org/licenses/Apache-2.0)
+[![ChipFoundry Marketplace](https://img.shields.io/badge/ChipFoundry-Marketplace-6E40C9.svg)](https://platform.chipfoundry.io/marketplace)
+
+</div>
+
+## Table of Contents
+- [Overview](#overview)
+- [Documentation & Resources](#documentation--resources)
+- [Prerequisites](#prerequisites)
+- [Project Structure](#project-structure)
+- [Starting Your Project](#starting-your-project)
+- [Development Flow](#development-flow)
+- [GPIO Configuration](#gpio-configuration)
+- [Local Precheck](#local-precheck)
+- [Checklist for Shuttle Submission](#checklist-for-shuttle-submission)
+
+## Overview
+This repository contains a user project designed for integration into the **Caravel chip user space**. Use it as a template for integrating custom RTL with Caravel's system-on-chip (SoC) utilities, including:
+
+* **IO Pads:** Configurable general-purpose input/output.
+* **Logic Analyzer Probes:** 128 signals for non-intrusive hardware debugging.
+* **Wishbone Port:** A 32-bit standard bus interface for communication between the RISC-V management core and your custom hardware.
+
+---
+
+## Documentation & Resources
+For detailed hardware specifications and register maps, refer to the following official documents:
+
+* **[Caravel Datasheet](https://github.com/chipfoundry/caravel/blob/main/docs/caravel_datasheet_2.pdf)**: Detailed electrical and physical specifications of the Caravel harness.
+* **[Caravel Technical Reference Manual (TRM)](https://github.com/chipfoundry/caravel/blob/main/docs/caravel_datasheet_2_register_TRM_r2.pdf)**: Complete register maps and programming guides for the management SoC.
+* **[ChipFoundry Marketplace](https://platform.chipfoundry.io/marketplace)**: Access additional IP blocks, EDA tools, and shuttle services.
+
+---
+
+## Prerequisites
+Ensure your environment meets the following requirements:
+
+1. **Docker** [Linux](https://docs.docker.com/desktop/setup/install/linux/ubuntu/) | [Windows](https://docs.docker.com/desktop/setup/install/windows-install/) | [Mac](https://docs.docker.com/desktop/setup/install/mac-install/)
+2. **Python 3.8+** with `pip`.
+3. **Git**: For repository management.
+
+---
+
+## Project Structure
+A successful Caravel project requires a specific directory layout for the automated tools to function:
+
+| Directory | Description |
+| :--- | :--- |
+| `openlane/` | Configuration files for hardening macros and the wrapper. |
+| `verilog/rtl/` | Source Verilog code for the project. |
+| `verilog/gl/` | Gate-level netlists (generated after hardening). |
+| `verilog/dv/` | Design Verification (cocotb and Verilog testbenches). |
+| `gds/` | Final GDSII binary files for fabrication. |
+| `lef/` | Library Exchange Format files for the macros. |
+
+---
+
+## Starting Your Project
+
+### 1. Repository Setup
+Create a new repository based on the `caravel_user_project` template and clone it to your local machine:
+
+```bash
+git clone <your-github-repo-URL>
+pip install chipfoundry-cli
+cd <project_name>
+```
+
+### 2. Project Initialization
+
+> [!IMPORTANT]
+> Run this first! Initialize your project configuration:
+
+```bash
+cf init
+```
+
+This creates `.cf/project.json` with project metadata. **This must be run before any other commands** (`cf setup`, `cf gpio-config`, `cf harden`, `cf precheck`, `cf verify`).
+
+### 3. Environment Setup
+Install the ChipFoundry CLI tool and set up the local environment (PDKs, OpenLane, and Caravel lite):
+
+```bash
+cf setup
+```
+
+The `cf setup` command installs:
+
+- Caravel Lite: The Caravel SoC template.
+- Management Core: RISC-V management area required for simulation.
+- OpenLane: The RTL-to-GDS hardening flow.
+- PDK: Skywater 130nm process design kit.
+- Timing Scripts: For Static Timing Analysis (STA).
+
+---
+
+## Development Flow
+
+### Hardening the Design
+Hardening is the process of synthesizing your RTL and performing Place & Route (P&R) to create a GDSII layout.
+
+#### Macro Hardening
+Create a subdirectory for each custom macro under `openlane/` containing your `config.tcl`.
+
+```bash
+cf harden --list         # List detected configurations
+cf harden <macro_name>   # Harden a specific macro
+```
+
+#### Integration
+Instantiate your module(s) in `verilog/rtl/user_project_wrapper.v`.
+
+Update `openlane/user_project_wrapper/config.json` environment variables (`VERILOG_FILES_BLACKBOX`, `EXTRA_LEFS`, `EXTRA_GDS_FILES`) to point to your new macros.
+
+#### Wrapper Hardening
+Finalize the top-level user project:
+
+```bash
+cf harden user_project_wrapper
+```
+
+### Verification
+
+#### 1. Simulation
+We use cocotb for functional verification. Ensure your file lists are updated in `verilog/includes/`.
+
+**Configure GPIO settings first (required before verification):**
+
+```bash
+cf gpio-config
+```
+
+This interactive command will:
+- Configure all GPIO pins interactively
+- Automatically update `verilog/rtl/user_defines.v`
+- Automatically run `gen_gpio_defaults.py` to generate GPIO defaults for simulation
+
+GPIO configuration is required before running any verification tests.
+
+Run RTL Simulation:
+
+```bash
+cf verify <test_name>
+```
+
+Run Gate-Level (GL) Simulation:
+
+```bash
+cf verify <test_name> --sim gl
+```
+
+Run all tests:
+
+```bash
+cf verify --all
+```
+
+#### 2. Static Timing Analysis (STA)
+Verify that your design meets timing constraints using OpenSTA:
+
+```bash
+make extract-parasitics
+make create-spef-mapping
+make caravel-sta
+```
+
+> [!NOTE]
+> Run `make setup-timing-scripts` if you need to update the STA environment.
+
+---
+
+## GPIO Configuration
+Configure the power-on default configuration for each GPIO using the interactive CLI tool.
+
+**Use the GPIO configuration command:**
+```bash
+cf gpio-config
+```
+
+This command will:
+- Present an interactive form for configuring GPIO pins 5-37 (GPIO 0-4 are fixed system pins)
+- Show available GPIO modes with descriptions
+- Allow selection by number, partial key, or full mode name
+- Save configuration to `.cf/project.json` (as hex values)
+- Automatically update `verilog/rtl/user_defines.v` with the new configuration
+- Automatically run `gen_gpio_defaults.py` to generate GPIO defaults for simulation (if Caravel is installed)
+
+**GPIO Pin Information:**
+- GPIO[0] to GPIO[4]: Preset system pins (do not change).
+- GPIO[5] to GPIO[37]: User-configurable pins.
+
+**Available GPIO Modes:**
+- Management modes: `mgmt_input_nopull`, `mgmt_input_pulldown`, `mgmt_input_pullup`, `mgmt_output`, `mgmt_bidirectional`, `mgmt_analog`
+- User modes: `user_input_nopull`, `user_input_pulldown`, `user_input_pullup`, `user_output`, `user_bidirectional`, `user_output_monitored`, `user_analog`
+
+> [!NOTE]
+> GPIO configuration is required before running `cf precheck` or `cf verify`. Invalid modes cannot be saved - all GPIOs must have valid configurations.
+
+---
+
+## Local Precheck
+Before submitting your design for fabrication, run the local precheck to ensure it complies with all shuttle requirements:
+
+> [!IMPORTANT]
+> GPIO configuration is required before running precheck. Make sure you've run `cf gpio-config` first.
+
+```bash
+cf precheck
+```
+
+You can also run specific checks or disable LVS:
+
+```bash
+cf precheck --disable-lvs                    # Skip LVS check
+cf precheck --checks license --checks makefile  # Run specific checks only
+```
+---
+
+## Checklist for Shuttle Submission
+- [ ] Top-level macro is named user_project_wrapper.
+- [ ] Full Chip Simulation passes for both RTL and GL.
+- [ ] Hardened Macros are LVS and DRC clean.
+- [ ] user_project_wrapper matches the required pin order/template.
+- [ ] Design passes the local cf precheck.
+- [ ] Documentation (this README) is updated with project-specific details.

docs/Makefile

@@ -0,0 +1,37 @@
+
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+# Minimal makefile for Sphinx documentation
+#
+
+# You can set these variables from the command line, and also
+# from the environment for the first two.
+SPHINXOPTS    ?=
+SPHINXBUILD   ?= sphinx-build
+SOURCEDIR     = source
+BUILDDIR      = build
+
+# Put it first so that "make" without argument is like "make help".
+help:
+	@$(SPHINXBUILD) -M help "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+
+.PHONY: help Makefile
+
+# Catch-all target: route all unknown targets to Sphinx using the new
+# "make mode" option.  $(O) is meant as a shortcut for $(SPHINXOPTS).
+%: Makefile
+	@$(SPHINXBUILD) -M $@ "$(SOURCEDIR)" "$(BUILDDIR)" $(SPHINXOPTS) $(O)
+

docs/environment.yml

@@ -0,0 +1,23 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+name: caravel-docs
+channels:
+- defaults
+dependencies:
+- python>=3.8
+- pip:
+  - -r file:requirements.txt

docs/requirements.txt

@@ -0,0 +1,7 @@
+git+https://github.com/SymbiFlow/sphinx_materialdesign_theme.git#egg=sphinx-symbiflow-theme
+
+docutils
+sphinx
+sphinx-autobuild
+sphinxcontrib-wavedrom
+sphinx-rtd-theme

docs/source/conf.py

@@ -0,0 +1,89 @@
+# SPDX-FileCopyrightText: 2020 Efabless Corporation
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+# Configuration file for the Sphinx documentation builder.
+#
+# This file only contains a selection of the most common options. For a full
+# list see the documentation:
+# https://www.sphinx-doc.org/en/master/usage/configuration.html
+
+# -- Path setup --------------------------------------------------------------
+
+# If extensions (or modules to document with autodoc) are in another directory,
+# add these directories to sys.path here. If the directory is relative to the
+# documentation root, use os.path.abspath to make it absolute, like shown here.
+#
+# import os
+# import sys
+# sys.path.insert(0, os.path.abspath('.'))
+
+
+# -- Project information -----------------------------------------------------
+
+project = 'CIIC Harness'
+copyright = '2020, efabless'
+author = 'efabless'
+
+
+# -- General configuration ---------------------------------------------------
+
+# Add any Sphinx extension module names here, as strings. They can be
+# extensions coming with Sphinx (named 'sphinx.ext.*') or your custom
+# ones.
+extensions = [
+  'sphinxcontrib.wavedrom',
+  'sphinx.ext.mathjax',
+  'sphinx.ext.todo'
+]
+
+# Add any paths that contain templates here, relative to this directory.
+templates_path = ['_templates']
+
+# List of patterns, relative to source directory, that match files and
+# directories to ignore when looking for source files.
+# This pattern also affects html_static_path and html_extra_path.
+exclude_patterns = [
+    'build',
+    'Thumbs.db',
+    # Files included in other rst files.
+    'introduction.rst',
+]
+
+
+# -- Options for HTML output -------------------------------------------------
+"""
+html_theme_options = {
+    'header_links' : [
+        ("Home", 'index', False, 'home'),
+        ("GitHub", "https://github.com/efabless/caravel", True, 'code'),
+    ],
+    'hide_symbiflow_links': True,
+    'license_url' : 'https://www.apache.org/licenses/LICENSE-2.0',
+}
+"""
+# The theme to use for HTML and HTML Help pages.  See the documentation for
+# a list of builtin themes.
+#
+html_theme = 'sphinx_rtd_theme'
+
+# Add any paths that contain custom static files (such as style sheets) here,
+# relative to this directory. They are copied after the builtin static files,
+# so a file named "default.css" will overwrite the builtin "default.css".
+html_static_path = ['_static']
+
+todo_include_todos = False
+
+numfig = True

lvs/user_project_wrapper/lvs_config.json

@@ -0,0 +1,30 @@
+{
+	"TOP_SOURCE": "user_project_wrapper",
+	"TOP_LAYOUT": "$TOP_SOURCE",
+	"EXTRACT_FLATGLOB": [
+		""
+	],
+	"EXTRACT_ABSTRACT": [
+		"*__fill_*",
+		"*__fakediode_*",
+		"*__tapvpwrvgnd_*"
+	],
+	"LVS_FLATTEN": [
+		""
+	],
+	"LVS_NOFLATTEN": [
+		""
+	],
+	"LVS_IGNORE": [
+		""
+	],
+	"LVS_SPICE_FILES": [
+		"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap*.spice",
+		"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
+	],
+	"LVS_VERILOG_FILES": [
+		"$UPRJ_ROOT/verilog/gl/user_proj_example.v",
+		"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
+	],
+	"LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
+}

openlane/.gitignore

@@ -0,0 +1,4 @@
+*/runs
+default.cvcrc
+.venv/
+.version-*

openlane/Makefile

@@ -0,0 +1,116 @@
+# Copyright 2025 UmbraLogic Technologies LLC
+#
+# Adapted from Caravel User Project
+#
+# Copyright 2020-2024 Efabless Corporation
+# SPDX-FileCopyrightText:
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#      http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+MAKEFLAGS += --warn-undefined-variables
+
+# set shell to bash
+SHELL := /bin/bash
+
+ifeq ($(origin LIBRELANE_RUN_TAG), undefined)
+export LIBRELANE_RUN_TAG := $(shell date '+%y_%m_%d_%H_%M')
+endif
+ifeq ($(origin CF_LIBRELANE_TAG), undefined)
+export CF_LIBRELANE_TAG := CI2511
+endif
+
+export CARAVEL_ROOT := $(CARAVEL_ROOT)
+export PDK := $(PDK)
+export PDK_ROOT := $(PDK_ROOT)
+
+designs = $(shell cd $(PROJECT_ROOT)/openlane && find * -maxdepth 0 -type d)
+current_design = null
+
+LIBRELANE_USE_NIX ?= 0
+
+librelane_args = \
+	--run-tag $(LIBRELANE_RUN_TAG) \
+	--manual-pdk \
+	--pdk-root $(PDK_ROOT) \
+	--pdk $(PDK)
+
+docker_mounts = \
+	-m $(PROJECT_ROOT) \
+	-m $(PDK_ROOT) \
+	-m $(CARAVEL_ROOT) \
+	-m $(HOME)/.ipm
+
+ifneq ($(MCW_ROOT),)
+export MCW_ROOT:=$(MCW_ROOT)
+docker_mounts += -m $(MCW_ROOT)
+endif
+
+ifeq ($(LIBRELANE_USE_NIX),1)
+ifeq ($(origin UPSTREAM_LIBRELANE_TAG), undefined)
+librelane_run = nix run github:chipfoundry/openlane-2/$(CF_LIBRELANE_TAG) --
+else
+librelane_run = nix run github:librelane/librelane/$(UPSTREAM_LIBRELANE_TAG) --
+endif
+else
+librelane_docker_args = $(shell test -t 0 || echo "--docker-no-tty")
+librelane_run = $(PROJECT_ROOT)/openlane/.venv/bin/python3 -m librelane $(docker_mounts) $(librelane_docker_args) --dockerized 
+endif
+
+list:
+	@echo $(designs)
+
+.PHONY: $(designs)
+$(designs) : export current_design=$@
+$(designs):
+	@config_dir="$(PROJECT_ROOT)/openlane/$@"; \
+	config=""; \
+	for ext in yaml json tcl; do \
+		if [ -f "$$config_dir/config.$$ext" ]; then \
+			config="$$config_dir/config.$$ext"; break; \
+		fi; \
+	done; \
+	if [ -n "$$config" ]; then \
+		cmd='$(librelane_run) $(librelane_args) --ef-save-views-to $(PROJECT_ROOT) --overwrite "$$config"'; \
+		echo "* Running LibreLane on $@ with $$config"; \
+		echo $$cmd; \
+		eval $$cmd; \
+	fi
+
+librelane: librelane-venv librelane-docker-image
+
+.PHONY: librelane-docker-image
+librelane-docker-image:
+	@echo "LibreLane will automatically pull the appropriate Docker image as needed."
+
+librelane-venv: $(PROJECT_ROOT)/openlane/.venv/manifest.txt
+$(PROJECT_ROOT)/openlane/.venv/manifest.txt: $(PROJECT_ROOT)/openlane/.version-$(CF_LIBRELANE_TAG)
+	rm -rf $(PROJECT_ROOT)/openlane/.venv
+	python3 -m venv $(PROJECT_ROOT)/openlane/.venv
+	PYTHONPATH= $(PROJECT_ROOT)/openlane/.venv/bin/python3 -m pip install --upgrade pip
+	PYTHONPATH= $(PROJECT_ROOT)/openlane/.venv/bin/python3 -m pip install "https://github.com/chipfoundry/openlane-2/tarball/$(CF_LIBRELANE_TAG)"
+	PYTHONPATH= $(PROJECT_ROOT)/openlane/.venv/bin/python3 -m pip freeze > $@
+	
+$(PROJECT_ROOT)/openlane/.version-$(CF_LIBRELANE_TAG):
+	echo "$(CF_LIBRELANE_TAG)" > $@
+	python3 -c 'import os; [os.remove(f) for f in os.listdir("$(@D)") if f.startswith(".version-") and f != os.path.basename("$@")]'
+
+.PHONY: librelane-nix
+librelane-nix:
+	@if ! command -v nix > /dev/null; then\
+		echo "Nix not found. Please install Nix using the LibreLane documentation:"; \
+		echo "	https://librelane.readthedocs.io/en/latest/getting_started/common/nix_installation/index.html"; \
+	else \
+		echo "Activating LibreLane Nix environment…"; \
+		nix develop github:chipfoundry/openlane-2/$(CF_LIBRELANE_TAG); \
+	fi

openlane/copy_views.sh

@@ -0,0 +1,57 @@
+#!/bin/bash
+
+# Check if the correct number of arguments are passed
+if [ "$#" -ne 3 ]; then
+    echo "Usage: $0 PROJECT_ROOT MACRO RUN_TAG"
+    exit 1
+fi
+
+# Assign arguments to variables
+PROJECT_ROOT=$1
+MACRO=$2
+RUN_TAG=$3
+
+# Create directory for timing reports
+mkdir -p "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/timing-reports"
+
+# Copy CSV files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/metrics.csv" "${PROJECT_ROOT}/signoff/${MACRO}/"
+
+# Copy DEF files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/def/${MACRO}.def" "${PROJECT_ROOT}/def/${MACRO}.def"
+
+# Copy SDC files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/sdc/${MACRO}.sdc" "${PROJECT_ROOT}/sdc/${MACRO}.sdc"
+
+# Copy GDS files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/gds/${MACRO}.gds" "${PROJECT_ROOT}/gds/${MACRO}.gds"
+
+# Copy LEF files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/lef/${MACRO}.lef" "${PROJECT_ROOT}/lef/${MACRO}.lef"
+
+# Copy MAG files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"magic-streamout/${MACRO}.mag" "${PROJECT_ROOT}/mag/${MACRO}.mag"
+
+# Copy Verilog files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/pnl/${MACRO}.pnl.v" "${PROJECT_ROOT}/verilog/gl/${MACRO}.v"
+
+
+# Copy SPEF files (nominal, minimum, maximum)
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/spef/nom/"* "${PROJECT_ROOT}/spef/multicorner/${MACRO}.nom.spef"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/spef/nom/"* "${PROJECT_ROOT}/spef/${MACRO}.spef"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/spef/min/"* "${PROJECT_ROOT}/spef/multicorner/${MACRO}.min.spef"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/spef/max/"* "${PROJECT_ROOT}/spef/multicorner/${MACRO}.max.spef"
+
+# Copy LIB files
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/final/lib/nom"*"tt"*"/"* "${PROJECT_ROOT}/lib/${MACRO}.lib"
+
+# Copy resolved.json
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/resolved.json" "${PROJECT_ROOT}/signoff/${MACRO}/"
+
+# Copy DRC, LVS reports, and logs
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"magic-drc/reports/"* "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"netgen-lvs/reports/"*".rpt" "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/"
+cp "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"netgen-lvs/netgen-lvs.log" "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/"
+
+# Copy STA post PnR summary report
+cp -r "${PROJECT_ROOT}/openlane/${MACRO}/runs/${RUN_TAG}/"*"openroad-stapostpnr/summary.rpt" "${PROJECT_ROOT}/signoff/${MACRO}/openlane-signoff/timing-reports/"

openlane/user_proj_example/base_user_proj_example.sdc

@@ -0,0 +1,145 @@
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+set ::env(IO_SYNC) 0
+# Clock network
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]

openlane/user_proj_example/config.json

@@ -0,0 +1,72 @@
+{
+    "DESIGN_NAME": "user_proj_example",
+    "FP_PDN_MULTILAYER": false,
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/user_proj_example.v"
+    ],
+    "CLOCK_PERIOD": 25,
+    "CLOCK_PORT": "wb_clk_i",
+    "CLOCK_NET": "counter.clk",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": [
+        0,
+        0,
+        2800,
+        1760
+    ],
+    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
+    "MAX_TRANSITION_CONSTRAINT": 1.0,
+    "MAX_FANOUT_CONSTRAINT": 16,
+    "PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
+    "GRT_RESIZER_SETUP_SLACK_MARGIN": 0.2,
+    "GRT_RESIZER_HOLD_SLACK_MARGIN": 0.2,
+    "PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
+    "CTS_CLK_MAX_WIRE_LENGTH": 500,
+    "MAGIC_DEF_LABELS": false,
+    "SYNTH_ABC_BUFFERING": false,
+    "RUN_HEURISTIC_DIODE_INSERTION": true,
+    "HEURISTIC_ANTENNA_THRESHOLD": 110,
+    "RUN_ANTENNA_REPAIR": true,
+    "RUN_POST_GRT_DESIGN_REPAIR": true,
+    "RUN_POST_GRT_RESIZER_TIMING": true,
+    "VDD_NETS": [
+        "vccd1"
+    ],
+    "GND_NETS": [
+        "vssd1"
+    ],
+    "FALLBACK_SDC_FILE": "dir::base_user_proj_example.sdc",
+    "MAGIC_DRC_USE_GDS": true,
+    "DPL_CELL_PADDING": 2,
+    "GPL_CELL_PADDING": 2,
+    "pdk::sky130*": {
+        "RT_MAX_LAYER": "met4",
+        "scl::sky130_fd_sc_hd": {
+            "CLOCK_PERIOD": 25
+        },
+        "scl::sky130_fd_sc_hdll": {
+            "CLOCK_PERIOD": 10
+        },
+        "scl::sky130_fd_sc_hs": {
+            "CLOCK_PERIOD": 8
+        },
+        "scl::sky130_fd_sc_ls": {
+            "CLOCK_PERIOD": 10,
+            "SYNTH_MAX_FANOUT": 5
+        },
+        "scl::sky130_fd_sc_ms": {
+            "CLOCK_PERIOD": 10
+        }
+    },
+    "pdk::gf180mcuC": {
+        "STD_CELL_LIBRARY": "gf180mcu_fd_sc_mcu7t5v0",
+        "CLOCK_PERIOD": 24.0,
+        "RT_MAX_LAYER": "Metal4",
+        "SYNTH_MAX_FANOUT": 4,
+        "PL_TARGET_DENSITY_PCT": 45
+    },
+    "meta": {
+        "version": 2
+    }
+}

openlane/user_proj_example/pin_order.cfg

@@ -0,0 +1,59 @@
+#BUS_SORT
+
+#S
+wb_.*
+wbs_.*
+la_.*
+irq.*
+
+#E
+io_in\[0\]
+io_out\[0\]
+io_oeb\[0\]
+io_in\[1\]
+io_out\[1\]
+io_oeb\[1\]
+io_in\[2\]
+io_out\[2\]
+io_oeb\[2\]
+io_in\[3\]
+io_out\[3\]
+io_oeb\[3\]
+io_in\[4\]
+io_out\[4\]
+io_oeb\[4\]
+io_in\[5\]
+io_out\[5\]
+io_oeb\[5\]
+io_in\[6\]
+io_out\[6\]
+io_oeb\[6\]
+io_in\[7\]
+io_out\[7\]
+io_oeb\[7\]
+
+#WR
+io_in\[8\]
+io_out\[8\]
+io_oeb\[8\]
+io_in\[9\]
+io_out\[9\]
+io_oeb\[9\]
+io_in\[10\]
+io_out\[10\]
+io_oeb\[10\]
+io_in\[11\]
+io_out\[11\]
+io_oeb\[11\]
+io_in\[12\]
+io_out\[12\]
+io_oeb\[12\]
+io_in\[13\]
+io_out\[13\]
+io_oeb\[13\]
+io_in\[14\]
+io_out\[14\]
+io_oeb\[14\]
+io_in\[15\]
+io_out\[15\]
+io_oeb\[15\]

openlane/user_project_wrapper/config.json

@@ -0,0 +1,107 @@
+{
+    "//": "Design files",
+    "VERILOG_FILES": [
+        "dir::../../verilog/rtl/defines.v",
+        "dir::../../verilog/rtl/user_project_wrapper.v"
+    ],
+    "PNR_SDC_FILE": "dir::signoff.sdc",
+    
+    "//": "Hardening strategy variables (this is for 1-Macro-First Hardening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info",
+    "SYNTH_ELABORATE_ONLY": true,
+    "RUN_POST_GPL_DESIGN_REPAIR": false,
+    "RUN_POST_CTS_RESIZER_TIMING": false,
+    "DESIGN_REPAIR_BUFFER_INPUT_PORTS": false,
+    "FP_PDN_ENABLE_RAILS": false,
+    "RUN_ANTENNA_REPAIR": false,
+    "RUN_FILL_INSERTION": false,
+    "RUN_TAP_ENDCAP_INSERTION": false,
+    "RUN_CTS": false,
+    "RUN_IRDROP_REPORT": false,
+    "ERROR_ON_SYNTH_CHECKS": false,
+
+    "//": "Macros configurations",
+    "MACROS": {
+        "user_proj_example": {
+            "gds": [
+                "dir::../../gds/user_proj_example.gds"
+            ],
+            "lef": [
+                "dir::../../lef/user_proj_example.lef"
+            ],
+            "instances": {
+                "mprj": {
+                    "location": [60, 15],
+                    "orientation": "N"
+                }
+            },
+            "nl": [
+                "dir::../../verilog/gl/user_proj_example.v"
+            ],
+            "spef": {
+                "min_*": [
+                    "dir::../../spef/multicorner/user_proj_example.min.spef"
+                ],
+                "nom_*": [
+                    "dir::../../spef/multicorner/user_proj_example.nom.spef"
+                ],
+                "max_*": [
+                    "dir::../../spef/multicorner/user_proj_example.max.spef"
+                ]
+            },
+            "lib": {
+                "*": "dir::../../lib/user_proj_example.lib"
+            }
+        }
+    },
+    "PDN_MACRO_CONNECTIONS": ["mprj vccd2 vssd2 vccd1 vssd1"],
+
+    "//": "PDN configurations",
+    "FP_PDN_VOFFSET": 5,
+    "FP_PDN_HOFFSET": 5,
+    "FP_PDN_VWIDTH": 3.1,
+    "FP_PDN_HWIDTH": 3.1,
+    "FP_PDN_VSPACING": 15.5,
+    "FP_PDN_HSPACING": 15.5,
+    "FP_PDN_VPITCH": 180,
+    "FP_PDN_HPITCH": 180,
+    "ERROR_ON_PDN_VIOLATIONS": false,
+
+    "//": "Magic variables",
+    "MAGIC_DRC_USE_GDS": true,
+
+    "DRT_THREADS": 1,
+    "MAX_TRANSITION_CONSTRAINT": 1.5,
+
+    "//": "Fixed configurations for caravel. You should NOT edit this section",
+    "DESIGN_NAME": "user_project_wrapper",
+    "FP_SIZING": "absolute",
+    "DIE_AREA": [0, 0, 2920, 3520],
+    "FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
+    "VDD_NETS": [
+        "vccd1",
+        "vccd2",
+        "vdda1",
+        "vdda2"
+    ],
+    "GND_NETS": [
+        "vssd1",
+        "vssd2",
+        "vssa1",
+        "vssa2"
+    ],
+    "FP_PDN_CORE_RING": true,
+    "FP_PDN_CORE_RING_VWIDTH": 3.1,
+    "FP_PDN_CORE_RING_HWIDTH": 3.1,
+    "FP_PDN_CORE_RING_VOFFSET": 12.45,
+    "FP_PDN_CORE_RING_HOFFSET": 12.45,
+    "FP_PDN_CORE_RING_VSPACING": 1.7,
+    "FP_PDN_CORE_RING_HSPACING": 1.7,
+    "CLOCK_PORT": "wb_clk_i",
+    "SIGNOFF_SDC_FILE": "dir::signoff.sdc",
+    "MAGIC_DEF_LABELS": false,
+    "CLOCK_PERIOD": 25,
+    "MAGIC_ZEROIZE_ORIGIN": false,
+    "meta": {
+        "version": 2
+    }
+}

openlane/user_project_wrapper/signoff.sdc

@@ -0,0 +1,145 @@
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+set ::env(IO_SYNC) 0
+# Clock network
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]

openlane/user_project_wrapper/vsrc/upw_vccd1_vsrc.loc

@@ -0,0 +1,3 @@
+2911.7,3148.92,24,1.8
+2911.7,3198.92,24,1.8
+2911.7,932.65,24,1.8

openlane/user_project_wrapper/vsrc/upw_vccd2_vsrc.loc

@@ -0,0 +1,3 @@
+8.30,3169.21,24,1.8
+8.30,3219.21,24,1.8
+8.30,839.94,24,1.8

openlane/user_project_wrapper/vsrc/upw_vdda1_vsrc.loc

@@ -0,0 +1,4 @@
+2911.70,1126.15,24,3.3
+2911.70,1176.15,24,3.3
+2911.70,2702.81,24,3.3
+2911.70,2752.81,24,3.3

openlane/user_project_wrapper/vsrc/upw_vdda2_vsrc.loc

@@ -0,0 +1,2 @@
+8.30,1024.44,24,3.3
+8.30,1074.44,24,3.3

openlane/user_project_wrapper/vsrc/upw_vssa1_vsrc.loc

@@ -0,0 +1,4 @@
+2911.7,684.15,24,0.0
+2911.7,734.15,24,0.0
+2552.97,3511.70,24,0.0
+2602.97,3511.70,24,0.0

openlane/user_project_wrapper/vsrc/upw_vssa2_vsrc.loc

@@ -0,0 +1,2 @@
+8.30,2747.21,24,0.0
+8.30,2797.21,24,0.0

openlane/user_project_wrapper/vsrc/upw_vssd1_vsrc.loc

@@ -0,0 +1,3 @@
+2911.7,907.15,24,0.0
+2911.7,957.15,24,0.0
+2911.7,3174.42,24,0.0

openlane/user_project_wrapper/vsrc/upw_vssd2_vsrc.loc

@@ -0,0 +1,3 @@
+8.30,814.44,24,0.0
+8.30,864.44,24,0.0
+8.30,3194.71,24,0.0

sdc/user_proj_example.sdc

@@ -0,0 +1,145 @@
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+set ::env(IO_SYNC) 0
+# Clock network
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]

sdc/user_project_wrapper.sdc

@@ -0,0 +1,145 @@
+# generated by get_cup_sdc.py
+# Date: 2023/06/20
+
+### Note:
+# - input clock transition and latency are set for wb_clk_i port.
+#   If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
+# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
+#   As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
+
+#------------------------------------------#
+# Pre-defined Constraints
+#------------------------------------------#
+
+set ::env(IO_SYNC) 0
+# Clock network
+if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
+	set clk_input $::env(CLOCK_PORT)
+	create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
+} else {
+	set clk_input __VIRTUAL_CLK__
+	create_clock -name clk -period $::env(CLOCK_PERIOD)
+	puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
+}
+if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
+	set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
+}
+
+# Clock non-idealities
+set_propagated_clock [all_clocks]
+set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
+set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
+puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
+
+# Maximum transition time for the design nets
+set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
+
+# Maximum fanout
+set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
+puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
+
+# Timing paths delays derate
+set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
+set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
+puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
+
+# Reset input delay
+set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
+
+# Multicycle paths
+set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_ack_o}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_cyc_i}]
+set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
+set_multicycle_path -hold 1  -through [get_ports {wbs_stb_i}]
+
+#------------------------------------------#
+# Retrieved Constraints
+#------------------------------------------#
+
+# Clock source latency
+set usr_clk_max_latency 4.57
+set usr_clk_min_latency 4.11
+set clk_max_latency 5.57
+set clk_min_latency 4.65
+set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
+set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
+puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
+
+# Clock input Transition
+set usr_clk_tran 0.13
+set clk_tran 0.61
+set_input_transition $clk_tran [get_ports $clk_input]
+puts "\[INFO\]: Setting clock transition: $clk_tran"
+
+# Input delays
+set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
+set_input_delay -min 0.3  -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
+set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
+set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
+set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
+set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
+set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
+set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
+if { $::env(IO_SYNC) } {
+	set in_ext_delay 4
+	puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
+	set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+	set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
+}
+
+# Input Transition
+set_input_transition -max 0.14  [get_ports {wbs_we_i}]
+set_input_transition -max 0.15  [get_ports {wbs_stb_i}]
+set_input_transition -max 0.17  [get_ports {wbs_cyc_i}]
+set_input_transition -max 0.18  [get_ports {wbs_sel_i[*]}]
+set_input_transition -max 0.38  [get_ports {io_in[*]}]
+set_input_transition -max 0.84  [get_ports {wbs_dat_i[*]}]
+set_input_transition -max 0.86  [get_ports {la_data_in[*]}]
+set_input_transition -max 0.92  [get_ports {wbs_adr_i[*]}]
+set_input_transition -max 0.97  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.05  [get_ports {io_in[*]}]
+set_input_transition -min 0.06  [get_ports {la_oenb[*]}]
+set_input_transition -min 0.07  [get_ports {la_data_in[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_adr_i[*]}]
+set_input_transition -min 0.07  [get_ports {wbs_dat_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_cyc_i}]
+set_input_transition -min 0.09  [get_ports {wbs_sel_i[*]}]
+set_input_transition -min 0.09  [get_ports {wbs_we_i}]
+set_input_transition -min 0.15  [get_ports {wbs_stb_i}]
+
+# Output delays
+set_output_delay -max 0.7  -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -max 1.0  -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
+set_output_delay -min 0    -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
+set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
+set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
+if { $::env(IO_SYNC) } {
+	set out_ext_delay 4
+	puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
+	set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+	set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
+	set_output_delay -min [expr $out_ext_delay + 3.9]  -clock [get_clocks {clk}] [get_ports {io_out[*]}]
+}
+
+# Output loads
+set_load 0.19 [all_outputs]

signoff/caravel/openlane-signoff/.gitignore

@@ -0,0 +1 @@
+/timing

signoff/user_proj_example/OPENLANE_VERSION

@@ -0,0 +1 @@
+2.0.0-b10

signoff/user_proj_example/PDK_SOURCES

@@ -0,0 +1 @@
+open_pdks e3b630d9b7c0e23615367d52c4f78b2d2ede58ac

signoff/user_proj_example/metrics.csv

@@ -0,0 +1,287 @@
+Metric,Value
+design__lint_error__count,0
+design__lint_timing_construct__count,0
+design__lint_warning__count,8
+design__inferred_latch__count,0
+design__instance__count,70590
+design__instance__area,95369
+design__instance_unmapped__count,0
+synthesis__check_error__count,0
+design__max_slew_violation__count__corner:nom_tt_025C_1v80,4
+design__max_fanout_violation__count__corner:nom_tt_025C_1v80,14
+design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
+power__internal__total,0.00019559991778805852
+power__switching__total,0.000429551990237087
+power__leakage__total,1.919598524580124E-8
+power__total,0.000625171116553247
+clock__skew__worst_hold__corner:nom_tt_025C_1v80,-2.096730848291461
+clock__skew__worst_setup__corner:nom_tt_025C_1v80,3.154773864771945
+timing__hold__ws__corner:nom_tt_025C_1v80,0.3478915032298054
+timing__setup__ws__corner:nom_tt_025C_1v80,7.060046969096608
+timing__hold__tns__corner:nom_tt_025C_1v80,0.0
+timing__setup__tns__corner:nom_tt_025C_1v80,0.0
+timing__hold__wns__corner:nom_tt_025C_1v80,0
+timing__setup__wns__corner:nom_tt_025C_1v80,0.0
+timing__hold_vio__count__corner:nom_tt_025C_1v80,0
+timing__hold_r2r__ws__corner:nom_tt_025C_1v80,1.019479
+timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
+timing__setup_vio__count__corner:nom_tt_025C_1v80,0
+timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
+timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
+design__max_slew_violation__count__corner:nom_ss_100C_1v60,174
+design__max_fanout_violation__count__corner:nom_ss_100C_1v60,14
+design__max_cap_violation__count__corner:nom_ss_100C_1v60,1
+clock__skew__worst_hold__corner:nom_ss_100C_1v60,-2.0973783303777345
+clock__skew__worst_setup__corner:nom_ss_100C_1v60,3.0085152998174016
+timing__hold__ws__corner:nom_ss_100C_1v60,1.0258354456252161
+timing__setup__ws__corner:nom_ss_100C_1v60,2.4240024007463363
+timing__hold__tns__corner:nom_ss_100C_1v60,0.0
+timing__setup__tns__corner:nom_ss_100C_1v60,0.0
+timing__hold__wns__corner:nom_ss_100C_1v60,0
+timing__setup__wns__corner:nom_ss_100C_1v60,0.0
+timing__hold_vio__count__corner:nom_ss_100C_1v60,0
+timing__hold_r2r__ws__corner:nom_ss_100C_1v60,2.235596
+timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
+timing__setup_vio__count__corner:nom_ss_100C_1v60,0
+timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
+timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
+design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
+design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,14
+design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
+clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-2.0964635065795703
+clock__skew__worst_setup__corner:nom_ff_n40C_1v95,3.25268488017196
+timing__hold__ws__corner:nom_ff_n40C_1v95,0.25673464081342046
+timing__setup__ws__corner:nom_ff_n40C_1v95,8.431948711247525
+timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
+timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
+timing__hold__wns__corner:nom_ff_n40C_1v95,0
+timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
+timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
+timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.587006
+timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
+timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
+timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
+timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
+design__max_slew_violation__count,192
+design__max_fanout_violation__count,14
+design__max_cap_violation__count,1
+clock__skew__worst_hold,-2.094480648201511
+clock__skew__worst_setup,3.0075507380263278
+timing__hold__ws,0.24338487469856057
+timing__setup__ws,2.391910737178117
+timing__hold__tns,0.0
+timing__setup__tns,0.0
+timing__hold__wns,0
+timing__setup__wns,0.0
+timing__hold_vio__count,0
+timing__hold_r2r__ws,0.571341
+timing__hold_r2r_vio__count,0
+timing__setup_vio__count,0
+timing__setup_r2r__ws,inf
+timing__setup_r2r_vio__count,0
+design__die__bbox,0.0 0.0 2800.0 1760.0
+design__core__bbox,5.52 10.88 2794.04 1748.96
+design__io,543
+design__die__area,4.928E+6
+design__core__area,4.84667E+6
+design__instance__count__stdcell,70590
+design__instance__area__stdcell,95369
+design__instance__count__macros,0
+design__instance__area__macros,0
+design__instance__utilization,0.0196772
+design__instance__utilization__stdcell,0.0196772
+design__instance__count__class:buffer,32
+design__instance__count__class:inverter,7
+design__instance__count__class:sequential_cell,33
+design__instance__count__class:multi_input_combinational_cell,273
+flow__warnings__count,1
+flow__errors__count,0
+design__instance__count__class:fill_cell,485362
+design__instance__count__class:tap_cell,69228
+design__power_grid_violation__count__net:vccd1,0
+design__power_grid_violation__count__net:vssd1,0
+design__power_grid_violation__count,0
+timing__drv__floating__nets,0
+timing__drv__floating__pins,0
+design__instance__displacement__total,0
+design__instance__displacement__mean,0
+design__instance__displacement__max,0
+route__wirelength__estimated,101712
+design__violations,0
+design__instance__count__class:timing_repair_buffer,362
+design__instance__count__class:clock_buffer,11
+design__instance__count__setup_buffer,0
+design__instance__count__hold_buffer,0
+antenna__violating__nets,4
+antenna__violating__pins,4
+route__antenna_violation__count,4
+design__instance__count__class:antenna_cell,644
+antenna_diodes_count,2
+route__net,1060
+route__net__special,2
+route__drc_errors__iter:1,198
+route__wirelength__iter:1,102911
+route__drc_errors__iter:2,82
+route__wirelength__iter:2,102825
+route__drc_errors__iter:3,84
+route__wirelength__iter:3,102834
+route__drc_errors__iter:4,5
+route__wirelength__iter:4,102805
+route__drc_errors__iter:5,0
+route__wirelength__iter:5,102803
+route__drc_errors,0
+route__wirelength,102803
+route__vias,4853
+route__vias__singlecut,4853
+route__vias__multicut,0
+design__disconnected_pin__count,286
+design__critical_disconnected_pin__count,0
+route__wirelength__max,3004.91
+timing__unannotated_net__count__corner:nom_tt_025C_1v80,420
+timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
+timing__unannotated_net__count__corner:nom_ss_100C_1v60,420
+timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
+timing__unannotated_net__count__corner:nom_ff_n40C_1v95,420
+timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
+design__max_slew_violation__count__corner:min_tt_025C_1v80,0
+design__max_fanout_violation__count__corner:min_tt_025C_1v80,14
+design__max_cap_violation__count__corner:min_tt_025C_1v80,0
+clock__skew__worst_hold__corner:min_tt_025C_1v80,-2.0946271976449062
+clock__skew__worst_setup__corner:min_tt_025C_1v80,3.166766494223121
+timing__hold__ws__corner:min_tt_025C_1v80,0.4132969639063154
+timing__setup__ws__corner:min_tt_025C_1v80,7.087754583861198
+timing__hold__tns__corner:min_tt_025C_1v80,0.0
+timing__setup__tns__corner:min_tt_025C_1v80,0.0
+timing__hold__wns__corner:min_tt_025C_1v80,0
+timing__setup__wns__corner:min_tt_025C_1v80,0.0
+timing__hold_vio__count__corner:min_tt_025C_1v80,0
+timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.992008
+timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
+timing__setup_vio__count__corner:min_tt_025C_1v80,0
+timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
+timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
+timing__unannotated_net__count__corner:min_tt_025C_1v80,420
+timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
+design__max_slew_violation__count__corner:min_ss_100C_1v60,120
+design__max_fanout_violation__count__corner:min_ss_100C_1v60,14
+design__max_cap_violation__count__corner:min_ss_100C_1v60,0
+clock__skew__worst_hold__corner:min_ss_100C_1v60,-2.095250254823947
+clock__skew__worst_setup__corner:min_ss_100C_1v60,3.037091553101025
+timing__hold__ws__corner:min_ss_100C_1v60,1.141694771038144
+timing__setup__ws__corner:min_ss_100C_1v60,2.494424293279187
+timing__hold__tns__corner:min_ss_100C_1v60,0.0
+timing__setup__tns__corner:min_ss_100C_1v60,0.0
+timing__hold__wns__corner:min_ss_100C_1v60,0
+timing__setup__wns__corner:min_ss_100C_1v60,0.0
+timing__hold_vio__count__corner:min_ss_100C_1v60,0
+timing__hold_r2r__ws__corner:min_ss_100C_1v60,2.180077
+timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
+timing__setup_vio__count__corner:min_ss_100C_1v60,0
+timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
+timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
+timing__unannotated_net__count__corner:min_ss_100C_1v60,420
+timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
+design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
+design__max_fanout_violation__count__corner:min_ff_n40C_1v95,14
+design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
+clock__skew__worst_hold__corner:min_ff_n40C_1v95,-2.094480648201511
+clock__skew__worst_setup__corner:min_ff_n40C_1v95,3.2570613794588086
+timing__hold__ws__corner:min_ff_n40C_1v95,0.3001150524152958
+timing__setup__ws__corner:min_ff_n40C_1v95,8.453670003294032
+timing__hold__tns__corner:min_ff_n40C_1v95,0.0
+timing__setup__tns__corner:min_ff_n40C_1v95,0.0
+timing__hold__wns__corner:min_ff_n40C_1v95,0
+timing__setup__wns__corner:min_ff_n40C_1v95,0.0
+timing__hold_vio__count__corner:min_ff_n40C_1v95,0
+timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.571341
+timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
+timing__setup_vio__count__corner:min_ff_n40C_1v95,0
+timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
+timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
+timing__unannotated_net__count__corner:min_ff_n40C_1v95,420
+timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
+design__max_slew_violation__count__corner:max_tt_025C_1v80,12
+design__max_fanout_violation__count__corner:max_tt_025C_1v80,14
+design__max_cap_violation__count__corner:max_tt_025C_1v80,0
+clock__skew__worst_hold__corner:max_tt_025C_1v80,-2.1012268075791374
+clock__skew__worst_setup__corner:max_tt_025C_1v80,3.160448436855897
+timing__hold__ws__corner:max_tt_025C_1v80,0.3314753010342061
+timing__setup__ws__corner:max_tt_025C_1v80,7.0523784364040365
+timing__hold__tns__corner:max_tt_025C_1v80,0.0
+timing__setup__tns__corner:max_tt_025C_1v80,0.0
+timing__hold__wns__corner:max_tt_025C_1v80,0
+timing__setup__wns__corner:max_tt_025C_1v80,0.0
+timing__hold_vio__count__corner:max_tt_025C_1v80,0
+timing__hold_r2r__ws__corner:max_tt_025C_1v80,1.026777
+timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
+timing__setup_vio__count__corner:max_tt_025C_1v80,0
+timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
+timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
+timing__unannotated_net__count__corner:max_tt_025C_1v80,420
+timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
+design__max_slew_violation__count__corner:max_ss_100C_1v60,192
+design__max_fanout_violation__count__corner:max_ss_100C_1v60,14
+design__max_cap_violation__count__corner:max_ss_100C_1v60,1
+clock__skew__worst_hold__corner:max_ss_100C_1v60,-2.101982647435679
+clock__skew__worst_setup__corner:max_ss_100C_1v60,3.0075507380263278
+timing__hold__ws__corner:max_ss_100C_1v60,1.0005818679036624
+timing__setup__ws__corner:max_ss_100C_1v60,2.391910737178117
+timing__hold__tns__corner:max_ss_100C_1v60,0.0
+timing__setup__tns__corner:max_ss_100C_1v60,0.0
+timing__hold__wns__corner:max_ss_100C_1v60,0
+timing__setup__wns__corner:max_ss_100C_1v60,0.0
+timing__hold_vio__count__corner:max_ss_100C_1v60,0
+timing__hold_r2r__ws__corner:max_ss_100C_1v60,2.250683
+timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
+timing__setup_vio__count__corner:max_ss_100C_1v60,0
+timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
+timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
+timing__unannotated_net__count__corner:max_ss_100C_1v60,420
+timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
+design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
+design__max_fanout_violation__count__corner:max_ff_n40C_1v95,14
+design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
+clock__skew__worst_hold__corner:max_ff_n40C_1v95,-2.1008075873531826
+clock__skew__worst_setup__corner:max_ff_n40C_1v95,3.259567374940867
+timing__hold__ws__corner:max_ff_n40C_1v95,0.24338487469856057
+timing__setup__ws__corner:max_ff_n40C_1v95,8.420825164404606
+timing__hold__tns__corner:max_ff_n40C_1v95,0.0
+timing__setup__tns__corner:max_ff_n40C_1v95,0.0
+timing__hold__wns__corner:max_ff_n40C_1v95,0
+timing__setup__wns__corner:max_ff_n40C_1v95,0.0
+timing__hold_vio__count__corner:max_ff_n40C_1v95,0
+timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.591791
+timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
+timing__setup_vio__count__corner:max_ff_n40C_1v95,0
+timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
+timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
+timing__unannotated_net__count__corner:max_ff_n40C_1v95,420
+timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
+timing__unannotated_net__count,420
+timing__unannotated_net_filtered__count,0
+design_powergrid__voltage__worst__net:vccd1__corner:nom_tt_025C_1v80,1.79983
+design_powergrid__drop__average__net:vccd1__corner:nom_tt_025C_1v80,1.8
+design_powergrid__drop__worst__net:vccd1__corner:nom_tt_025C_1v80,0.000166719
+design_powergrid__voltage__worst__net:vssd1__corner:nom_tt_025C_1v80,0.000205177
+design_powergrid__drop__average__net:vssd1__corner:nom_tt_025C_1v80,2.51703E-7
+design_powergrid__drop__worst__net:vssd1__corner:nom_tt_025C_1v80,0.000205177
+design_powergrid__voltage__worst,0.000205177
+design_powergrid__voltage__worst__net:vccd1,1.79983
+design_powergrid__drop__worst,0.000205177
+design_powergrid__drop__worst__net:vccd1,0.000166719
+design_powergrid__voltage__worst__net:vssd1,0.000205177
+design_powergrid__drop__worst__net:vssd1,0.000205177
+ir__voltage__worst,1.8000000000000000444089209850062616169452667236328125
+ir__drop__avg,2.30999999999999990605605015847601180212222971022129058837890625E-7
+ir__drop__worst,0.0001669999999999999935017258589908806243329308927059173583984375
+design__xor_difference__count,0
+magic__drc_error__count,0
+klayout__drc_error__count,0
+magic__illegal_overlap__count,0
+design__lvs_device_difference__count,0
+design__lvs_net_difference__count,0
+design__lvs_property_fail__count,0
+design__lvs_error__count,0
+design__lvs_unmatched_device__count,0
+design__lvs_unmatched_net__count,0
+design__lvs_unmatched_pin__count,0

signoff/user_proj_example/openlane-signoff/antenna_summary.rpt

@@ -0,0 +1,8 @@
+┏━━━━━━━┳━━━━━━━━━┳━━━━━━━━━━┳━━━━━━━━┳━━━━━━━━━━┳━━━━━━━┓
+┃ P / R ┃ Partial ┃ Required ┃ Net    ┃ Pin      ┃ Layer ┃
+┡━━━━━━━╇━━━━━━━━━╇━━━━━━━━━━╇━━━━━━━━╇━━━━━━━━━━╇━━━━━━━┩
+│ 7.34  │ 2936.33 │ 400.00   │ net87  │ _221_/C  │ met1  │
+│ 5.72  │ 2286.22 │ 400.00   │ net125 │ _475_/A  │ met1  │
+│ 4.46  │ 1782.36 │ 400.00   │ net6   │ hold2/A  │ met1  │
+│ 4.41  │ 1764.67 │ 400.00   │ _078_  │ hold44/A │ met1  │
+└───────┴─────────┴──────────┴────────┴──────────┴───────┘

signoff/user_proj_example/openlane-signoff/drc.klayout.xml

@@ -0,0 +1,3 @@
+<!-- Despite the name, this is the Magic DRC report in KLayout format. -->
+<?xml version='1.0' encoding='utf8'?>
+<report-database><cells><cell><name>user_proj_example</name></cell></cells><categories></categories><items></items></report-database>

signoff/user_proj_example/openlane-signoff/drc.rpt

@@ -0,0 +1,5 @@
+user_proj_example
+----------------------------------------
+[INFO] COUNT: 0
+[INFO] Should be divided by 3 or 4
+

signoff/user_proj_example/openlane-signoff/flow.log

@@ -0,0 +1,334 @@
+Starting…
+Running 'Verilator.Lint' at 'user_proj_example/runs/25_11_11_03_19/01-verilator-lint'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/01-verilator-lint/verilator-lint.log'[/repr.filename]…
+Running 'Checker.LintTimingConstructs' at 'user_proj_example/runs/25_11_11_03_19/02-checker-linttimingconstructs'…
+Check for Lint Timing Errors clear.
+Running 'Checker.LintErrors' at 'user_proj_example/runs/25_11_11_03_19/03-checker-linterrors'…
+Check for Lint errors clear.
+Running 'Checker.LintWarnings' at 'user_proj_example/runs/25_11_11_03_19/04-checker-lintwarnings'…
+8 Lint warnings found.
+Running 'Yosys.JsonHeader' at 'user_proj_example/runs/25_11_11_03_19/05-yosys-jsonheader'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/05-yosys-jsonheader/yosys-jsonheader.log'[/repr.filename]…
+Running 'Yosys.Synthesis' at 'user_proj_example/runs/25_11_11_03_19/06-yosys-synthesis'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/06-yosys-synthesis/yosys-synthesis.log'[/repr.filename]…
+Parsing synthesis checks…
+Running 'Checker.YosysUnmappedCells' at 'user_proj_example/runs/25_11_11_03_19/07-checker-yosysunmappedcells'…
+Check for Unmapped Yosys instances clear.
+Running 'Checker.YosysSynthChecks' at 'user_proj_example/runs/25_11_11_03_19/08-checker-yosyssynthchecks'…
+Check for Yosys check errors clear.
+Running 'Checker.NetlistAssignStatements' at 'user_proj_example/runs/25_11_11_03_19/09-checker-netlistassignstatements'…
+Running 'OpenROAD.CheckSDCFiles' at 'user_proj_example/runs/25_11_11_03_19/10-openroad-checksdcfiles'…
+'PNR_SDC_FILE' is not defined. Using generic fallback SDC for OpenROAD PnR steps.
+'SIGNOFF_SDC_FILE' is not defined. Using generic fallback SDC for OpenROAD PnR steps.
+Running 'OpenROAD.CheckMacroInstances' at 'user_proj_example/runs/25_11_11_03_19/11-openroad-checkmacroinstances'…
+No macros found, skipping instance check…
+Running 'OpenROAD.STAPrePNR' at 'user_proj_example/runs/25_11_11_03_19/12-openroad-staprepnr'…
+Starting STA for the nom_tt_025C_1v80 timing corner…
+Starting STA for the nom_ss_100C_1v60 timing corner…
+Starting STA for the nom_ff_n40C_1v95 timing corner…
+Skipping corner min_tt_025C_1v80 for STA (identical to nom_tt_025C_1v80 at this stage)…
+Skipping corner min_ss_100C_1v60 for STA (identical to nom_ss_100C_1v60 at this stage)…
+Skipping corner min_ff_n40C_1v95 for STA (identical to nom_ff_n40C_1v95 at this stage)…
+Skipping corner max_tt_025C_1v80 for STA (identical to nom_tt_025C_1v80 at this stage)…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/12-openroad-staprepnr/nom_ff_n40C_1v95/sta.log'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/12-openroad-staprepnr/nom_tt_025C_1v80/sta.log'[/repr.filename]…
+Skipping corner max_ss_100C_1v60 for STA (identical to nom_ss_100C_1v60 at this stage)…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/12-openroad-staprepnr/nom_ss_100C_1v60/sta.log'[/repr.filename]…
+Skipping corner max_ff_n40C_1v95 for STA (identical to nom_ff_n40C_1v95 at this stage)…
+Finished STA for the nom_ff_n40C_1v95 timing corner.
+Finished STA for the nom_tt_025C_1v80 timing corner.
+Finished STA for the nom_ss_100C_1v60 timing corner.
+Running 'OpenROAD.Floorplan' at 'user_proj_example/runs/25_11_11_03_19/13-openroad-floorplan'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/13-openroad-floorplan/openroad-floorplan.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'Odb.CheckMacroAntennaProperties' at 'user_proj_example/runs/25_11_11_03_19/14-odb-checkmacroantennaproperties'…
+No cells provided, skipping…
+Running 'Odb.SetPowerConnections' at 'user_proj_example/runs/25_11_11_03_19/15-odb-setpowerconnections'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/15-odb-setpowerconnections/odb-setpowerconnections.log'[/repr.filename]…
+Running 'Odb.ManualMacroPlacement' at 'user_proj_example/runs/25_11_11_03_19/16-odb-manualmacroplacement'…
+No instances found, skipping 'Odb.ManualMacroPlacement'…
+Running 'OpenROAD.CutRows' at 'user_proj_example/runs/25_11_11_03_19/17-openroad-cutrows'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/17-openroad-cutrows/openroad-cutrows.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.TapEndcapInsertion' at 'user_proj_example/runs/25_11_11_03_19/18-openroad-tapendcapinsertion'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/18-openroad-tapendcapinsertion/openroad-tapendcapinsertion.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'Odb.AddPDNObstructions' at 'user_proj_example/runs/25_11_11_03_19/19-odb-addpdnobstructions'…
+'PDN_OBSTRUCTIONS' is not defined. Skipping 'Odb.AddPDNObstructions'…
+Running 'OpenROAD.GeneratePDN' at 'user_proj_example/runs/25_11_11_03_19/20-openroad-generatepdn'…
+'FP_PDN_CFG' not explicitly set, setting it to /nix/store/pqxyc4xmydcs5adig47yyc29r3svp5nx-python3-3.11.9-env/lib/python3.11/site-packages/librelane/scripts/openroad/common/pdn_cfg.tcl…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/20-openroad-generatepdn/openroad-generatepdn.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'Odb.RemovePDNObstructions' at 'user_proj_example/runs/25_11_11_03_19/21-odb-removepdnobstructions'…
+'PDN_OBSTRUCTIONS' is not defined. Skipping 'Odb.RemovePDNObstructions'…
+Running 'Odb.AddRoutingObstructions' at 'user_proj_example/runs/25_11_11_03_19/22-odb-addroutingobstructions'…
+'ROUTING_OBSTRUCTIONS' is not defined. Skipping 'Odb.AddRoutingObstructions'…
+Running 'OpenROAD.GlobalPlacementSkipIO' at 'user_proj_example/runs/25_11_11_03_19/23-openroad-globalplacementskipio'…
+'PL_TARGET_DENSITY_PCT' not explicitly set, using dynamically calculated target density: 21.8437800…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/23-openroad-globalplacementskipio/openroad-globalplacementskipio.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.IOPlacement' at 'user_proj_example/runs/25_11_11_03_19/24-openroad-ioplacement'…
+FP_PIN_ORDER_CFG is set. Skipping 'OpenROAD.IOPlacement'…
+Running 'Odb.CustomIOPlacement' at 'user_proj_example/runs/25_11_11_03_19/25-odb-customioplacement'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/25-odb-customioplacement/odb-customioplacement.log'[/repr.filename]…
+Running 'Odb.ApplyDEFTemplate' at 'user_proj_example/runs/25_11_11_03_19/26-odb-applydeftemplate'…
+No DEF template provided, skipping…
+Running 'OpenROAD.GlobalPlacement' at 'user_proj_example/runs/25_11_11_03_19/27-openroad-globalplacement'…
+'PL_TARGET_DENSITY_PCT' not explicitly set, using dynamically calculated target density: 21.8437800…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/27-openroad-globalplacement/openroad-globalplacement.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'Odb.WriteVerilogHeader' at 'user_proj_example/runs/25_11_11_03_19/28-odb-writeverilogheader'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/28-odb-writeverilogheader/odb-writeverilogheader.log'[/repr.filename]…
+Running 'Checker.PowerGridViolations' at 'user_proj_example/runs/25_11_11_03_19/29-checker-powergridviolations'…
+Check for power grid violations (as reported by OpenROAD PSM- you may ignore these if LVS passes) clear.
+Running 'OpenROAD.STAMidPNR' at 'user_proj_example/runs/25_11_11_03_19/30-openroad-stamidpnr'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/30-openroad-stamidpnr/openroad-stamidpnr.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+[GRT-0097] No global routing found for nets.
+Running 'OpenROAD.RepairDesignPostGPL' at 'user_proj_example/runs/25_11_11_03_19/31-openroad-repairdesignpostgpl'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/31-openroad-repairdesignpostgpl/openroad-repairdesignpostgpl.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'Odb.ManualGlobalPlacement' at 'user_proj_example/runs/25_11_11_03_19/32-odb-manualglobalplacement'…
+'MANUAL_GLOBAL_PLACEMENTS' not set, skipping…
+Running 'OpenROAD.DetailedPlacement' at 'user_proj_example/runs/25_11_11_03_19/33-openroad-detailedplacement'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/33-openroad-detailedplacement/openroad-detailedplacement.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.CTS' at 'user_proj_example/runs/25_11_11_03_19/34-openroad-cts'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/34-openroad-cts/openroad-cts.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+[CTS-0041] Net "wb_clk_i" has 1 sinks. Skipping...
+[RSZ-0065] max wire length less than 5786u increases wire delays.
+Running 'OpenROAD.STAMidPNR-1' at 'user_proj_example/runs/25_11_11_03_19/35-openroad-stamidpnr-1'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/35-openroad-stamidpnr-1/openroad-stamidpnr-1.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+[GRT-0097] No global routing found for nets.
+Running 'OpenROAD.ResizerTimingPostCTS' at 'user_proj_example/runs/25_11_11_03_19/36-openroad-resizertimingpostcts'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/36-openroad-resizertimingpostcts/openroad-resizertimingpostcts.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.STAMidPNR-2' at 'user_proj_example/runs/25_11_11_03_19/37-openroad-stamidpnr-2'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/37-openroad-stamidpnr-2/openroad-stamidpnr-2.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+[GRT-0097] No global routing found for nets.
+Running 'OpenROAD.GlobalRouting' at 'user_proj_example/runs/25_11_11_03_19/38-openroad-globalrouting'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/38-openroad-globalrouting/openroad-globalrouting.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.CheckAntennas' at 'user_proj_example/runs/25_11_11_03_19/39-openroad-checkantennas'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/39-openroad-checkantennas/openroad-checkantennas.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.RepairDesignPostGRT' at 'user_proj_example/runs/25_11_11_03_19/40-openroad-repairdesignpostgrt'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/40-openroad-repairdesignpostgrt/openroad-repairdesignpostgrt.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'Odb.DiodesOnPorts' at 'user_proj_example/runs/25_11_11_03_19/41-odb-diodesonports'…
+'DIODE_ON_PORTS' is set to 'none': skipping…
+Running 'Odb.HeuristicDiodeInsertion' at 'user_proj_example/runs/25_11_11_03_19/42-odb-heuristicdiodeinsertion'…
+Running 'Odb.FuzzyDiodePlacement' at 'user_proj_example/runs/25_11_11_03_19/42-odb-heuristicdiodeinsertion/1-odb-fuzzydiodeplacement'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/42-odb-heuristicdiodeinsertion/1-odb-fuzzydiodeplacement/odb-fuzzydiodeplacement.log'[/repr.filename]…
+Running 'OpenROAD.DetailedPlacement' at 'user_proj_example/runs/25_11_11_03_19/42-odb-heuristicdiodeinsertion/2-openroad-detailedplacement'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/42-odb-heuristicdiodeinsertion/2-openroad-detailedplacement/openroad-detailedplacement.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.GlobalRouting' at 'user_proj_example/runs/25_11_11_03_19/42-odb-heuristicdiodeinsertion/3-openroad-globalrouting'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/42-odb-heuristicdiodeinsertion/3-openroad-globalrouting/openroad-globalrouting.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.RepairAntennas' at 'user_proj_example/runs/25_11_11_03_19/43-openroad-repairantennas'…
+Running 'DiodeInsertion' at 'user_proj_example/runs/25_11_11_03_19/43-openroad-repairantennas/1-diodeinsertion'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/43-openroad-repairantennas/1-diodeinsertion/diodeinsertion.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.CheckAntennas' at 'user_proj_example/runs/25_11_11_03_19/43-openroad-repairantennas/2-openroad-checkantennas'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/43-openroad-repairantennas/2-openroad-checkantennas/openroad-checkantennas.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.ResizerTimingPostGRT' at 'user_proj_example/runs/25_11_11_03_19/44-openroad-resizertimingpostgrt'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/44-openroad-resizertimingpostgrt/openroad-resizertimingpostgrt.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.STAMidPNR-3' at 'user_proj_example/runs/25_11_11_03_19/45-openroad-stamidpnr-3'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/45-openroad-stamidpnr-3/openroad-stamidpnr-3.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'OpenROAD.DetailedRouting' at 'user_proj_example/runs/25_11_11_03_19/46-openroad-detailedrouting'…
+Running TritonRoute with 8 threads…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/46-openroad-detailedrouting/openroad-detailedrouting.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer mcon
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via2
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via3
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
+[DRT-0349] LEF58_ENCLOSURE with no CUTCLASS is not supported. Skipping for layer via4
+Running 'Odb.RemoveRoutingObstructions' at 'user_proj_example/runs/25_11_11_03_19/47-odb-removeroutingobstructions'…
+'ROUTING_OBSTRUCTIONS' is not defined. Skipping 'Odb.RemoveRoutingObstructions'…
+Running 'OpenROAD.CheckAntennas-1' at 'user_proj_example/runs/25_11_11_03_19/48-openroad-checkantennas-1'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/48-openroad-checkantennas-1/openroad-checkantennas-1.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'Checker.TrDRC' at 'user_proj_example/runs/25_11_11_03_19/49-checker-trdrc'…
+Check for Routing DRC errors clear.
+Running 'Odb.ReportDisconnectedPins' at 'user_proj_example/runs/25_11_11_03_19/50-odb-reportdisconnectedpins'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/50-odb-reportdisconnectedpins/odb-reportdisconnectedpins.log'[/repr.filename]…
+Running 'Checker.DisconnectedPins' at 'user_proj_example/runs/25_11_11_03_19/51-checker-disconnectedpins'…
+Check for critical disconnected pins clear.
+Running 'Odb.ReportWireLength' at 'user_proj_example/runs/25_11_11_03_19/52-odb-reportwirelength'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/52-odb-reportwirelength/odb-reportwirelength.log'[/repr.filename]…
+Running 'Checker.WireLength' at 'user_proj_example/runs/25_11_11_03_19/53-checker-wirelength'…
+Threshold for Threshold-surpassing long wires is not set. The checker will be skipped.
+Running 'OpenROAD.FillInsertion' at 'user_proj_example/runs/25_11_11_03_19/54-openroad-fillinsertion'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/54-openroad-fillinsertion/openroad-fillinsertion.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+Running 'Odb.CellFrequencyTables' at 'user_proj_example/runs/25_11_11_03_19/55-odb-cellfrequencytables'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/55-odb-cellfrequencytables/buffer_list.txt'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/55-odb-cellfrequencytables/odb-cellfrequencytables.log'[/repr.filename]…
+Running 'OpenROAD.RCX' at 'user_proj_example/runs/25_11_11_03_19/56-openroad-rcx'…
+Running RCX for corners matching nom_* (/home/marwan/caravel_user_project/openlane/user_proj_example/runs/25_11_11_03_19/56-openroad-rcx/nom/rcx.log)…
+Running RCX for corners matching max_* (/home/marwan/caravel_user_project/openlane/user_proj_example/runs/25_11_11_03_19/56-openroad-rcx/max/rcx.log)…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/56-openroad-rcx/max/rcx.log'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/56-openroad-rcx/nom/rcx.log'[/repr.filename]…
+Running RCX for corners matching min_* (/home/marwan/caravel_user_project/openlane/user_proj_example/runs/25_11_11_03_19/56-openroad-rcx/min/rcx.log)…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/56-openroad-rcx/min/rcx.log'[/repr.filename]…
+Finished RCX for corners matching max_*.
+Finished RCX for corners matching nom_*.
+Finished RCX for corners matching min_*.
+Running 'OpenROAD.STAPostPNR' at 'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr'…
+Starting STA for the nom_tt_025C_1v80 timing corner…
+Starting STA for the nom_ss_100C_1v60 timing corner…
+Starting STA for the nom_ff_n40C_1v95 timing corner…
+Starting STA for the min_tt_025C_1v80 timing corner…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/nom_ss_100C_1v60/sta.log'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/nom_tt_025C_1v80/sta.log'[/repr.filename]…
+Starting STA for the min_ss_100C_1v60 timing corner…
+Starting STA for the min_ff_n40C_1v95 timing corner…
+Starting STA for the max_tt_025C_1v80 timing corner…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/nom_ff_n40C_1v95/sta.log'[/repr.filename]…
+Starting STA for the max_ss_100C_1v60 timing corner…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/min_ss_100C_1v60/sta.log'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/min_ff_n40C_1v95/sta.log'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/min_tt_025C_1v80/sta.log'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/max_ss_100C_1v60/sta.log'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/max_tt_025C_1v80/sta.log'[/repr.filename]…
+Finished STA for the nom_ff_n40C_1v95 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/nom_ff_n40C_1v95/filter_unannotated.log'[/repr.filename]…
+Finished STA for the min_ss_100C_1v60 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/min_ss_100C_1v60/filter_unannotated.log'[/repr.filename]…
+Finished STA for the nom_tt_025C_1v80 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/nom_tt_025C_1v80/filter_unannotated.log'[/repr.filename]…
+Finished STA for the max_ss_100C_1v60 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/max_ss_100C_1v60/filter_unannotated.log'[/repr.filename]…
+Finished STA for the max_tt_025C_1v80 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/max_tt_025C_1v80/filter_unannotated.log'[/repr.filename]…
+Finished STA for the min_ff_n40C_1v95 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/min_ff_n40C_1v95/filter_unannotated.log'[/repr.filename]…
+Finished STA for the min_tt_025C_1v80 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/min_tt_025C_1v80/filter_unannotated.log'[/repr.filename]…
+Finished STA for the nom_ss_100C_1v60 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/nom_ss_100C_1v60/filter_unannotated.log'[/repr.filename]…
+Starting STA for the max_ff_n40C_1v95 timing corner…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/max_ff_n40C_1v95/sta.log'[/repr.filename]…
+Finished STA for the max_ff_n40C_1v95 timing corner.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/57-openroad-stapostpnr/max_ff_n40C_1v95/filter_unannotated.log'[/repr.filename]…
+Running 'OpenROAD.IRDropReport' at 'user_proj_example/runs/25_11_11_03_19/58-openroad-irdropreport'…
+'VSRC_LOC_FILES' was not given a value, which may make the results of IR drop analysis inaccurate. If you are not integrating a top-level chip for manufacture, you may ignore this warning, otherwise, see the documentation for 'VSRC_LOC_FILES'.
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/58-openroad-irdropreport/openroad-irdropreport.log'[/repr.filename]…
+[STA-0366] port 'user_irq[*]' not found.
+[STA-0366] port 'user_irq[*]' not found.
+[INFO PSM-0040] All shapes on net vccd1 are connected.
+########## IR report #################
+Net              : vccd1
+Corner           : nom_tt_025C_1v80
+Supply voltage   : 1.80e+00 V
+Worstcase voltage: 1.80e+00 V
+Average voltage  : 1.80e+00 V
+Average IR drop  : 2.31e-07 V
+Worstcase IR drop: 1.67e-04 V
+Percentage drop  : 0.01 %
+######################################
+[INFO PSM-0040] All shapes on net vssd1 are connected.
+########## IR report #################
+Net              : vssd1
+Corner           : nom_tt_025C_1v80
+Supply voltage   : 0.00e+00 V
+Worstcase voltage: 2.05e-04 V
+Average voltage  : 2.52e-07 V
+Average IR drop  : 2.52e-07 V
+Worstcase IR drop: 2.05e-04 V
+Percentage drop  : 0.01 %
+######################################
+
+Running 'Magic.StreamOut' at 'user_proj_example/runs/25_11_11_03_19/59-magic-streamout'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/59-magic-streamout/magic-streamout.log'[/repr.filename]…
+Running 'KLayout.StreamOut' at 'user_proj_example/runs/25_11_11_03_19/60-klayout-streamout'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/60-klayout-streamout/klayout-streamout.log'[/repr.filename]…
+Running 'Magic.WriteLEF' at 'user_proj_example/runs/25_11_11_03_19/61-magic-writelef'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/61-magic-writelef/magic-writelef.log'[/repr.filename]…
+Running 'Odb.CheckDesignAntennaProperties' at 'user_proj_example/runs/25_11_11_03_19/62-odb-checkdesignantennaproperties'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/62-odb-checkdesignantennaproperties/odb-checkdesignantennaproperties.log'[/repr.filename]…
+Cell 'user_proj_example' has (286) input pin(s) without antenna gate information. They might not be connected to a gate.
+Cell 'user_proj_example' has (131) output pin(s) without antenna diffusion information. They might not be driven.
+Running 'KLayout.XOR' at 'user_proj_example/runs/25_11_11_03_19/63-klayout-xor'…
+Running XOR with 8 threads…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/63-klayout-xor/klayout-xor.log'[/repr.filename]…
+Running 'Checker.XOR' at 'user_proj_example/runs/25_11_11_03_19/64-checker-xor'…
+Check for XOR differences clear.
+Running 'Magic.DRC' at 'user_proj_example/runs/25_11_11_03_19/65-magic-drc'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/65-magic-drc/magic-drc.log'[/repr.filename]…
+Running 'KLayout.DRC' at 'user_proj_example/runs/25_11_11_03_19/66-klayout-drc'…
+Running KLayout DRC with 8 threads…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/66-klayout-drc/klayout-drc.log'[/repr.filename]…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/66-klayout-drc/xml_drc_report_to_json.log'[/repr.filename]…
+Running 'Checker.MagicDRC' at 'user_proj_example/runs/25_11_11_03_19/67-checker-magicdrc'…
+Check for Magic DRC errors clear.
+Running 'Checker.KLayoutDRC' at 'user_proj_example/runs/25_11_11_03_19/68-checker-klayoutdrc'…
+Check for KLayout DRC errors clear.
+Running 'Magic.SpiceExtraction' at 'user_proj_example/runs/25_11_11_03_19/69-magic-spiceextraction'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/69-magic-spiceextraction/magic-spiceextraction.log'[/repr.filename]…
+Running 'Checker.IllegalOverlap' at 'user_proj_example/runs/25_11_11_03_19/70-checker-illegaloverlap'…
+Check for Magic Illegal Overlap errors clear.
+Running 'Netgen.LVS' at 'user_proj_example/runs/25_11_11_03_19/71-netgen-lvs'…
+Logging subprocess to [repr.filename]'user_proj_example/runs/25_11_11_03_19/71-netgen-lvs/netgen-lvs.log'[/repr.filename]…
+Running 'Checker.LVS' at 'user_proj_example/runs/25_11_11_03_19/72-checker-lvs'…
+Check for LVS errors clear.
+Gating variable for step 'Yosys.EQY' set to 'False'- the step will be skipped.
+Skipping step 'Equivalence Check'…
+Running 'Checker.SetupViolations' at 'user_proj_example/runs/25_11_11_03_19/73-checker-setupviolations'…
+No setup violations found
+Running 'Checker.HoldViolations' at 'user_proj_example/runs/25_11_11_03_19/74-checker-holdviolations'…
+No hold violations found
+Running 'Checker.MaxSlewViolations' at 'user_proj_example/runs/25_11_11_03_19/75-checker-maxslewviolations'…
+Max Slew violations found in the following corners:
+* max_ss_100C_1v60
+* max_tt_025C_1v80
+* min_ss_100C_1v60
+* nom_ss_100C_1v60
+* nom_tt_025C_1v80
+No max slew violations found
+Running 'Checker.MaxCapViolations' at 'user_proj_example/runs/25_11_11_03_19/76-checker-maxcapviolations'…
+Max Cap violations found in the following corners:
+* max_ss_100C_1v60
+* nom_ss_100C_1v60
+No max cap violations found
+Running 'Misc.ReportManufacturability' at 'user_proj_example/runs/25_11_11_03_19/77-misc-reportmanufacturability'…
+Saving views to '/home/marwan/caravel_user_project/openlane/user_proj_example/runs/25_11_11_03_19/final'…
+Flow complete.

signoff/user_proj_example/openlane-signoff/magic-drc.log

@@ -0,0 +1,219 @@
+
+Magic 8.3 revision 489 - Compiled on Thu Aug 22 13:45:15 UTC 2024.
+Starting magic under Tcl interpreter
+Using the terminal as the console.
+Using NULL graphics device.
+Processing system .magicrc file
+Sourcing design .magicrc for technology sky130A ...
+2 Magic internal units = 1 Lambda
+Input style sky130(): scaleFactor=2, multiplier=2
+The following types are not handled by extraction and will be treated as non-electrical types:
+    ubm 
+Scaled tech values by 2 / 1 to match internal grid scaling
+Loading sky130A Device Generator Menu ...
+Loading "/nix/store/pqxyc4xmydcs5adig47yyc29r3svp5nx-python3-3.11.9-env/lib/python3.11/site-packages/librelane/scripts/magic/wrapper.tcl" from command line.
+Warning: Calma reading is not undoable!  I hope that's OK.
+Library written using GDS-II Release 3.0
+Library name: user_proj_example
+Reading "sky130_ef_sc_hd__decap_40_12".
+Reading "sky130_fd_sc_hd__decap_3".
+Reading "sky130_fd_sc_hd__fill_1".
+Reading "sky130_fd_sc_hd__tapvpwrvgnd_1".
+Reading "sky130_fd_sc_hd__fill_2".
+Reading "sky130_fd_sc_hd__fill_4".
+Reading "sky130_fd_sc_hd__buf_4".
+Reading "sky130_fd_sc_hd__fill_8".
+Reading "sky130_fd_sc_hd__diode_2".
+Reading "sky130_fd_sc_hd__buf_12".
+Reading "sky130_fd_sc_hd__clkbuf_8".
+Reading "sky130_fd_sc_hd__dlygate4sd3_1".
+Reading "sky130_fd_sc_hd__clkbuf_4".
+Reading "sky130_fd_sc_hd__buf_2".
+Reading "sky130_fd_sc_hd__dfxtp_1".
+Reading "sky130_fd_sc_hd__mux2_1".
+Reading "sky130_fd_sc_hd__dfxtp_2".
+Reading "sky130_fd_sc_hd__conb_1".
+Reading "sky130_fd_sc_hd__and2_4".
+Reading "sky130_fd_sc_hd__and2_2".
+Reading "sky130_fd_sc_hd__nand2_8".
+Reading "sky130_fd_sc_hd__nor2_2".
+Reading "sky130_fd_sc_hd__inv_2".
+Reading "sky130_fd_sc_hd__buf_6".
+Reading "sky130_fd_sc_hd__nand3b_4".
+Reading "sky130_fd_sc_hd__a211o_1".
+Reading "sky130_fd_sc_hd__nor2_1".
+Reading "sky130_fd_sc_hd__and3_1".
+Reading "sky130_fd_sc_hd__a21oi_4".
+Reading "sky130_fd_sc_hd__and2b_1".
+Reading "sky130_fd_sc_hd__buf_1".
+Reading "sky130_fd_sc_hd__a22o_1".
+Reading "sky130_fd_sc_hd__a31o_1".
+Reading "sky130_fd_sc_hd__o21a_1".
+Reading "sky130_fd_sc_hd__a221o_1".
+Reading "sky130_fd_sc_hd__a32o_1".
+Reading "sky130_fd_sc_hd__and2_1".
+Reading "sky130_fd_sc_hd__nand2_1".
+Reading "sky130_fd_sc_hd__o2bb2a_1".
+Reading "sky130_fd_sc_hd__a21oi_1".
+Reading "sky130_fd_sc_hd__o21ai_1".
+Reading "sky130_fd_sc_hd__a32o_4".
+Reading "sky130_fd_sc_hd__a21o_1".
+Reading "sky130_fd_sc_hd__or3b_2".
+Reading "sky130_fd_sc_hd__and2b_2".
+Reading "sky130_fd_sc_hd__a31o_4".
+Reading "sky130_fd_sc_hd__clkbuf_1".
+Reading "sky130_fd_sc_hd__or3b_4".
+Reading "sky130_fd_sc_hd__and4_1".
+Reading "sky130_fd_sc_hd__a41o_4".
+Reading "sky130_fd_sc_hd__and3b_4".
+Reading "sky130_fd_sc_hd__buf_8".
+Reading "sky130_fd_sc_hd__clkbuf_16".
+Reading "sky130_fd_sc_hd__dfxtp_4".
+Reading "sky130_fd_sc_hd__nor2_8".
+Reading "sky130_fd_sc_hd__or2_1".
+Reading "sky130_fd_sc_hd__o31a_1".
+Reading "sky130_fd_sc_hd__o211a_1".
+Reading "sky130_fd_sc_hd__o32a_1".
+Reading "sky130_fd_sc_hd__a31oi_1".
+Reading "sky130_fd_sc_hd__o31ai_1".
+Reading "sky130_fd_sc_hd__o211ai_4".
+Reading "sky130_fd_sc_hd__a41oi_4".
+Reading "sky130_fd_sc_hd__and4_2".
+Reading "sky130_fd_sc_hd__xor2_1".
+Reading "sky130_fd_sc_hd__or2_2".
+Reading "sky130_fd_sc_hd__nor2_4".
+Reading "sky130_fd_sc_hd__or3_4".
+Reading "sky130_fd_sc_hd__nand2_2".
+Reading "sky130_fd_sc_hd__xnor2_1".
+Reading "sky130_fd_sc_hd__and3b_1".
+Reading "sky130_fd_sc_hd__a31o_2".
+Reading "sky130_fd_sc_hd__a21bo_1".
+Reading "sky130_fd_sc_hd__a21boi_1".
+Reading "sky130_fd_sc_hd__nand2b_1".
+Reading "sky130_fd_sc_hd__xnor2_2".
+Reading "sky130_fd_sc_hd__nand4_2".
+Reading "sky130_fd_sc_hd__a41o_1".
+Reading "sky130_fd_sc_hd__and4_4".
+Reading "sky130_fd_sc_hd__clkbuf_2".
+Reading "user_proj_example".
+    5000 uses
+    10000 uses
+    15000 uses
+    20000 uses
+    25000 uses
+    30000 uses
+    35000 uses
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+    45000 uses
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+    520000 uses
+    525000 uses
+    530000 uses
+    535000 uses
+    540000 uses
+    545000 uses
+    550000 uses
+    555000 uses
+[INFO] Loading user_proj_example
+
+DRC style is now "drc(full)"
+Loading DRC CIF style.
+No errors found.
+[INFO] COUNT: 0
+[INFO] Should be divided by 3 or 4
+[INFO] DRC Checking DONE (/home/marwan/caravel_user_project/openlane/user_proj_example/runs/25_11_11_03_19/65-magic-drc/reports/drc_violations.magic.rpt)
+[INFO] Saving mag view with DRC errors (/home/marwan/caravel_user_project/openlane/user_proj_example/runs/25_11_11_03_19/65-magic-drc/views/user_proj_example.drc.mag)
+[INFO] Saved

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/checks.rpt

@@ -0,0 +1,746 @@
+
+===========================================================================
+report_checks -unconstrained
+===========================================================================
+======================= max_ff_n40C_1v95 Corner ===================================
+
+Startpoint: wb_rst_i (input port clocked by clk)
+Endpoint: _305_ (rising edge-triggered flip-flop clocked by clk)
+Path Group: clk
+Path Type: max
+
+Fanout         Cap        Slew       Delay        Time   Description
+---------------------------------------------------------------------------------------------
+                                  0.000000    0.000000   clock clk (rise edge)
+                                  5.570000    5.570000   clock network delay (propagated)
+                                 12.500000   18.070000 v input external delay
+     2    0.004856    0.000000    0.000000   18.070000 v wb_rst_i (in)
+                                                         wb_rst_i (net)
+                      0.000181    0.000091   18.070089 v input37/A (sky130_fd_sc_hd__buf_4)
+     3    0.110424    0.098336    0.125718   18.195808 v input37/X (sky130_fd_sc_hd__buf_4)
+                                                         net37 (net)
+                      0.135287    0.046743   18.242552 v _153_/A1 (sky130_fd_sc_hd__a21oi_4)
+     1    0.005730    0.075903    0.116115   18.358665 ^ _153_/Y (sky130_fd_sc_hd__a21oi_4)
+                                                         _039_ (net)
+                      0.075904    0.000320   18.358986 ^ hold50/A (sky130_fd_sc_hd__dlygate4sd3_1)
+     1    0.005266    0.053893    0.393303   18.752289 ^ hold50/X (sky130_fd_sc_hd__dlygate4sd3_1)
+                                                         net324 (net)
+                      0.053893    0.000369   18.752659 ^ hold8/A (sky130_fd_sc_hd__dlygate4sd3_1)
+    15    0.064470    0.481229    0.688093   19.440752 ^ hold8/X (sky130_fd_sc_hd__dlygate4sd3_1)
+                                                         net282 (net)
+                      0.481325    0.006683   19.447435 ^ hold51/A (sky130_fd_sc_hd__dlygate4sd3_1)
+     7    0.045561    0.343535    0.616277   20.063711 ^ hold51/X (sky130_fd_sc_hd__dlygate4sd3_1)
+                                                         net325 (net)
+                      0.343539    0.001823   20.065535 ^ _160_/A (sky130_fd_sc_hd__nand2_2)
+     2    0.016516    0.100649    0.071001   20.136536 v _160_/Y (sky130_fd_sc_hd__nand2_2)
+                                                         _044_ (net)
+                      0.100708    0.001855   20.138390 v hold52/A (sky130_fd_sc_hd__dlygate4sd3_1)
+     5    0.049854    0.178902    0.528459   20.666849 v hold52/X (sky130_fd_sc_hd__dlygate4sd3_1)
+                                                         net326 (net)
+                      0.179036    0.004416   20.671265 v fanout124/A (sky130_fd_sc_hd__buf_6)
+    33    0.138553    0.086504    0.171376   20.842640 v fanout124/X (sky130_fd_sc_hd__buf_6)
+                                                         net124 (net)
+                      0.086895    0.005862   20.848503 v _161_/A (sky130_fd_sc_hd__inv_2)
+     2    0.007811    0.040688    0.060034   20.908535 ^ _161_/Y (sky130_fd_sc_hd__inv_2)
+                                                         _000_ (net)
+                      0.040691    0.000369   20.908905 ^ _233_/A2 (sky130_fd_sc_hd__a32o_1)
+     1    0.002588    0.036818    0.083903   20.992807 ^ _233_/X (sky130_fd_sc_hd__a32o_1)
+                                                         _009_ (net)
+                      0.036818    0.000108   20.992916 ^ hold157/A (sky130_fd_sc_hd__dlygate4sd3_1)
+     1    0.002569    0.035881    0.370500   21.363417 ^ hold157/X (sky130_fd_sc_hd__dlygate4sd3_1)
+                                                         net431 (net)
+                      0.035881    0.000187   21.363604 ^ hold41/A (sky130_fd_sc_hd__dlygate4sd3_1)
+     1    0.003126    0.039863    0.373847   21.737450 ^ hold41/X (sky130_fd_sc_hd__dlygate4sd3_1)
+                                                         net315 (net)
+                      0.039863    0.000234   21.737684 ^ hold158/A (sky130_fd_sc_hd__dlygate4sd3_1)
+     1    0.002185    0.033721    0.368708   22.106392 ^ hold158/X (sky130_fd_sc_hd__dlygate4sd3_1)
+                                                         net432 (net)
+                      0.033721    0.000158   22.106550 ^ _305_/D (sky130_fd_sc_hd__dfxtp_4)
+                                             22.106550   data arrival time
+
+                                 25.000000   25.000000   clock clk (rise edge)
+                                  4.650000   29.650000   clock source latency
+     2    0.032763    0.610000    0.000000   29.650000 ^ wb_clk_i (in)
+                                                         wb_clk_i (net)
+                      0.618803    0.004402   29.654400 ^ wire3/A (sky130_fd_sc_hd__buf_4)
+     3    0.049820    0.112641    0.158005   29.812407 ^ wire3/X (sky130_fd_sc_hd__buf_4)
+                                                         net274 (net)
+                      0.114199    0.010509   29.822914 ^ wire2/A (sky130_fd_sc_hd__buf_6)
+     3    0.112546    0.170016    0.169734   29.992649 ^ wire2/X (sky130_fd_sc_hd__buf_6)
+                                                         net273 (net)
+                      0.171907    0.014463   30.007113 ^ _155_/A1 (sky130_fd_sc_hd__mux2_1)
+     3    0.055033    0.362209    0.330900   30.338013 ^ _155_/X (sky130_fd_sc_hd__mux2_1)
+                                                         clk (net)
+                      0.362317    0.005212   30.343224 ^ wire1/A (sky130_fd_sc_hd__buf_4)
+     3    0.051820    0.114516    0.160306   30.503529 ^ wire1/X (sky130_fd_sc_hd__buf_4)
+                                                         net272 (net)
+                      0.116068    0.010619   30.514149 ^ clkbuf_0_clk/A (sky130_fd_sc_hd__clkbuf_16)
+     9    0.097281    0.088029    0.147494   30.661642 ^ clkbuf_0_clk/X (sky130_fd_sc_hd__clkbuf_16)
+                                                         clknet_0_clk (net)
+                      0.089284    0.008317   30.669960 ^ clkbuf_2_2__f_clk/A (sky130_fd_sc_hd__clkbuf_16)
+    21    0.068737    0.066371    0.123642   30.793602 ^ clkbuf_2_2__f_clk/X (sky130_fd_sc_hd__clkbuf_16)
+                                                         clknet_2_2__leaf_clk (net)
+                      0.071567    0.014406   30.808008 ^ _305_/CLK (sky130_fd_sc_hd__dfxtp_4)
+                                 -0.250000   30.558006   clock uncertainty
+                                  0.000000   30.558006   clock reconvergence pessimism
+                                 -0.030632   30.527376   library setup time
+                                             30.527376   data required time
+---------------------------------------------------------------------------------------------
+                                             30.527376   data required time
+                                            -22.106550   data arrival time
+---------------------------------------------------------------------------------------------
+                                              8.420825   slack (MET)
+
+
+
+
+===========================================================================
+report_checks --slack_max -0.01
+============================================================================
+======================= max_ff_n40C_1v95 Corner ===================================
+
+No paths found.
+
+
+===========================================================================
+ report_check_types -max_slew -max_cap -max_fanout -violators
+============================================================================
+======================= max_ff_n40C_1v95 Corner ===================================
+
+max fanout
+
+Pin                                   Limit Fanout  Slack
+---------------------------------------------------------
+fanout124/X                              16     33    -17 (VIOLATED)
+fanout125/X                              16     33    -17 (VIOLATED)
+_159_/Y                                  16     29    -13 (VIOLATED)
+_156_/X                                  16     27    -11 (VIOLATED)
+_195_/X                                  16     23     -7 (VIOLATED)
+_182_/X                                  16     21     -5 (VIOLATED)
+clkbuf_2_2__f_clk/X                      16     21     -5 (VIOLATED)
+_176_/Y                                  16     19     -3 (VIOLATED)
+_297_/Q                                  16     19     -3 (VIOLATED)
+clkbuf_2_1__f_clk/X                      16     19     -3 (VIOLATED)
+clkbuf_2_3__f_clk/X                      16     19     -3 (VIOLATED)
+clkbuf_2_0__f_clk/X                      16     17        (VIOLATED)
+hold140/X                                16     17        (VIOLATED)
+wire4/X                                  16     17        (VIOLATED)
+
+
+
+===========================================================================
+report_parasitic_annotation -report_unannotated
+============================================================================
+Found 420 unannotated drivers.
+ io_in[0]
+ io_in[10]
+ io_in[11]
+ io_in[12]
+ io_in[13]
+ io_in[14]
+ io_in[15]
+ io_in[1]
+ io_in[2]
+ io_in[3]
+ io_in[4]
+ io_in[5]
+ io_in[6]
+ io_in[7]
+ io_in[8]
+ io_in[9]
+ la_data_in[0]
+ la_data_in[100]
+ la_data_in[101]
+ la_data_in[102]
+ la_data_in[103]
+ la_data_in[104]
+ la_data_in[105]
+ la_data_in[106]
+ la_data_in[107]
+ la_data_in[108]
+ la_data_in[109]
+ la_data_in[10]
+ la_data_in[110]
+ la_data_in[111]
+ la_data_in[112]
+ la_data_in[113]
+ la_data_in[114]
+ la_data_in[115]
+ la_data_in[116]
+ la_data_in[117]
+ la_data_in[118]
+ la_data_in[119]
+ la_data_in[11]
+ la_data_in[120]
+ la_data_in[121]
+ la_data_in[122]
+ la_data_in[123]
+ la_data_in[124]
+ la_data_in[125]
+ la_data_in[126]
+ la_data_in[127]
+ la_data_in[12]
+ la_data_in[13]
+ la_data_in[14]
+ la_data_in[15]
+ la_data_in[16]
+ la_data_in[17]
+ la_data_in[18]
+ la_data_in[19]
+ la_data_in[1]
+ la_data_in[20]
+ la_data_in[21]
+ la_data_in[22]
+ la_data_in[23]
+ la_data_in[24]
+ la_data_in[25]
+ la_data_in[26]
+ la_data_in[27]
+ la_data_in[28]
+ la_data_in[29]
+ la_data_in[2]
+ la_data_in[30]
+ la_data_in[31]
+ la_data_in[32]
+ la_data_in[33]
+ la_data_in[34]
+ la_data_in[35]
+ la_data_in[36]
+ la_data_in[37]
+ la_data_in[38]
+ la_data_in[39]
+ la_data_in[3]
+ la_data_in[40]
+ la_data_in[41]
+ la_data_in[42]
+ la_data_in[43]
+ la_data_in[44]
+ la_data_in[45]
+ la_data_in[46]
+ la_data_in[47]
+ la_data_in[4]
+ la_data_in[5]
+ la_data_in[66]
+ la_data_in[67]
+ la_data_in[68]
+ la_data_in[69]
+ la_data_in[6]
+ la_data_in[70]
+ la_data_in[71]
+ la_data_in[72]
+ la_data_in[73]
+ la_data_in[74]
+ la_data_in[75]
+ la_data_in[76]
+ la_data_in[77]
+ la_data_in[78]
+ la_data_in[79]
+ la_data_in[7]
+ la_data_in[80]
+ la_data_in[81]
+ la_data_in[82]
+ la_data_in[83]
+ la_data_in[84]
+ la_data_in[85]
+ la_data_in[86]
+ la_data_in[87]
+ la_data_in[88]
+ la_data_in[89]
+ la_data_in[8]
+ la_data_in[90]
+ la_data_in[91]
+ la_data_in[92]
+ la_data_in[93]
+ la_data_in[94]
+ la_data_in[95]
+ la_data_in[96]
+ la_data_in[97]
+ la_data_in[98]
+ la_data_in[99]
+ la_data_in[9]
+ la_oenb[0]
+ la_oenb[100]
+ la_oenb[101]
+ la_oenb[102]
+ la_oenb[103]
+ la_oenb[104]
+ la_oenb[105]
+ la_oenb[106]
+ la_oenb[107]
+ la_oenb[108]
+ la_oenb[109]
+ la_oenb[10]
+ la_oenb[110]
+ la_oenb[111]
+ la_oenb[112]
+ la_oenb[113]
+ la_oenb[114]
+ la_oenb[115]
+ la_oenb[116]
+ la_oenb[117]
+ la_oenb[118]
+ la_oenb[119]
+ la_oenb[11]
+ la_oenb[120]
+ la_oenb[121]
+ la_oenb[122]
+ la_oenb[123]
+ la_oenb[124]
+ la_oenb[125]
+ la_oenb[126]
+ la_oenb[127]
+ la_oenb[12]
+ la_oenb[13]
+ la_oenb[14]
+ la_oenb[15]
+ la_oenb[16]
+ la_oenb[17]
+ la_oenb[18]
+ la_oenb[19]
+ la_oenb[1]
+ la_oenb[20]
+ la_oenb[21]
+ la_oenb[22]
+ la_oenb[23]
+ la_oenb[24]
+ la_oenb[25]
+ la_oenb[26]
+ la_oenb[27]
+ la_oenb[28]
+ la_oenb[29]
+ la_oenb[2]
+ la_oenb[30]
+ la_oenb[31]
+ la_oenb[32]
+ la_oenb[33]
+ la_oenb[34]
+ la_oenb[35]
+ la_oenb[36]
+ la_oenb[37]
+ la_oenb[38]
+ la_oenb[39]
+ la_oenb[3]
+ la_oenb[40]
+ la_oenb[41]
+ la_oenb[42]
+ la_oenb[43]
+ la_oenb[44]
+ la_oenb[45]
+ la_oenb[46]
+ la_oenb[47]
+ la_oenb[4]
+ la_oenb[5]
+ la_oenb[66]
+ la_oenb[67]
+ la_oenb[68]
+ la_oenb[69]
+ la_oenb[6]
+ la_oenb[70]
+ la_oenb[71]
+ la_oenb[72]
+ la_oenb[73]
+ la_oenb[74]
+ la_oenb[75]
+ la_oenb[76]
+ la_oenb[77]
+ la_oenb[78]
+ la_oenb[79]
+ la_oenb[7]
+ la_oenb[80]
+ la_oenb[81]
+ la_oenb[82]
+ la_oenb[83]
+ la_oenb[84]
+ la_oenb[85]
+ la_oenb[86]
+ la_oenb[87]
+ la_oenb[88]
+ la_oenb[89]
+ la_oenb[8]
+ la_oenb[90]
+ la_oenb[91]
+ la_oenb[92]
+ la_oenb[93]
+ la_oenb[94]
+ la_oenb[95]
+ la_oenb[96]
+ la_oenb[97]
+ la_oenb[98]
+ la_oenb[99]
+ la_oenb[9]
+ wbs_adr_i[0]
+ wbs_adr_i[10]
+ wbs_adr_i[11]
+ wbs_adr_i[12]
+ wbs_adr_i[13]
+ wbs_adr_i[14]
+ wbs_adr_i[15]
+ wbs_adr_i[16]
+ wbs_adr_i[17]
+ wbs_adr_i[18]
+ wbs_adr_i[19]
+ wbs_adr_i[1]
+ wbs_adr_i[20]
+ wbs_adr_i[21]
+ wbs_adr_i[22]
+ wbs_adr_i[23]
+ wbs_adr_i[24]
+ wbs_adr_i[25]
+ wbs_adr_i[26]
+ wbs_adr_i[27]
+ wbs_adr_i[28]
+ wbs_adr_i[29]
+ wbs_adr_i[2]
+ wbs_adr_i[30]
+ wbs_adr_i[31]
+ wbs_adr_i[3]
+ wbs_adr_i[4]
+ wbs_adr_i[5]
+ wbs_adr_i[6]
+ wbs_adr_i[7]
+ wbs_adr_i[8]
+ wbs_adr_i[9]
+ wbs_dat_i[16]
+ wbs_dat_i[17]
+ wbs_dat_i[18]
+ wbs_dat_i[19]
+ wbs_dat_i[20]
+ wbs_dat_i[21]
+ wbs_dat_i[22]
+ wbs_dat_i[23]
+ wbs_dat_i[24]
+ wbs_dat_i[25]
+ wbs_dat_i[26]
+ wbs_dat_i[27]
+ wbs_dat_i[28]
+ wbs_dat_i[29]
+ wbs_dat_i[30]
+ wbs_dat_i[31]
+ wbs_sel_i[2]
+ wbs_sel_i[3]
+ clkload0/X
+ clkload1/X
+ clkload2/X
+ user_proj_example_141/HI
+ user_proj_example_142/HI
+ user_proj_example_143/HI
+ user_proj_example_144/HI
+ user_proj_example_145/HI
+ user_proj_example_146/HI
+ user_proj_example_147/HI
+ user_proj_example_148/HI
+ user_proj_example_149/HI
+ user_proj_example_150/HI
+ user_proj_example_151/HI
+ user_proj_example_152/HI
+ user_proj_example_153/HI
+ user_proj_example_154/HI
+ user_proj_example_155/HI
+ user_proj_example_156/HI
+ user_proj_example_157/HI
+ user_proj_example_158/HI
+ user_proj_example_159/HI
+ user_proj_example_160/HI
+ user_proj_example_161/HI
+ user_proj_example_162/HI
+ user_proj_example_163/HI
+ user_proj_example_164/HI
+ user_proj_example_165/HI
+ user_proj_example_166/HI
+ user_proj_example_167/HI
+ user_proj_example_168/HI
+ user_proj_example_169/HI
+ user_proj_example_170/HI
+ user_proj_example_171/HI
+ user_proj_example_172/HI
+ user_proj_example_173/HI
+ user_proj_example_174/HI
+ user_proj_example_175/HI
+ user_proj_example_176/HI
+ user_proj_example_177/HI
+ user_proj_example_178/HI
+ user_proj_example_179/HI
+ user_proj_example_180/HI
+ user_proj_example_181/HI
+ user_proj_example_182/HI
+ user_proj_example_183/HI
+ user_proj_example_184/HI
+ user_proj_example_185/HI
+ user_proj_example_186/HI
+ user_proj_example_187/HI
+ user_proj_example_188/HI
+ user_proj_example_189/HI
+ user_proj_example_190/HI
+ user_proj_example_191/HI
+ user_proj_example_192/HI
+ user_proj_example_193/HI
+ user_proj_example_194/HI
+ user_proj_example_195/HI
+ user_proj_example_196/HI
+ user_proj_example_197/HI
+ user_proj_example_198/HI
+ user_proj_example_199/HI
+ user_proj_example_200/HI
+ user_proj_example_201/HI
+ user_proj_example_202/HI
+ user_proj_example_203/HI
+ user_proj_example_204/HI
+ user_proj_example_205/HI
+ user_proj_example_206/HI
+ user_proj_example_207/HI
+ user_proj_example_208/HI
+ user_proj_example_209/HI
+ user_proj_example_210/HI
+ user_proj_example_211/HI
+ user_proj_example_212/HI
+ user_proj_example_213/HI
+ user_proj_example_214/HI
+ user_proj_example_215/HI
+ user_proj_example_216/HI
+ user_proj_example_217/HI
+ user_proj_example_218/HI
+ user_proj_example_219/HI
+ user_proj_example_220/HI
+ user_proj_example_221/HI
+ user_proj_example_222/HI
+ user_proj_example_223/HI
+ user_proj_example_224/HI
+ user_proj_example_225/HI
+ user_proj_example_226/HI
+ user_proj_example_227/HI
+ user_proj_example_228/HI
+ user_proj_example_229/HI
+ user_proj_example_230/HI
+ user_proj_example_231/HI
+ user_proj_example_232/HI
+ user_proj_example_233/HI
+ user_proj_example_234/HI
+ user_proj_example_235/HI
+ user_proj_example_236/HI
+ user_proj_example_237/HI
+ user_proj_example_238/HI
+ user_proj_example_239/HI
+ user_proj_example_240/HI
+ user_proj_example_241/HI
+ user_proj_example_242/HI
+ user_proj_example_243/HI
+ user_proj_example_244/HI
+ user_proj_example_245/HI
+ user_proj_example_246/HI
+ user_proj_example_247/HI
+ user_proj_example_248/HI
+ user_proj_example_249/HI
+ user_proj_example_250/HI
+ user_proj_example_251/HI
+ user_proj_example_252/HI
+ user_proj_example_253/HI
+ user_proj_example_254/HI
+ user_proj_example_255/HI
+ user_proj_example_256/HI
+ user_proj_example_257/HI
+ user_proj_example_258/HI
+ user_proj_example_259/HI
+ user_proj_example_260/HI
+ user_proj_example_261/HI
+ user_proj_example_262/HI
+ user_proj_example_263/HI
+ user_proj_example_264/HI
+ user_proj_example_265/HI
+ user_proj_example_266/HI
+ user_proj_example_267/HI
+ user_proj_example_268/HI
+ user_proj_example_269/HI
+ user_proj_example_270/HI
+ user_proj_example_271/HI
+Found 0 partially unannotated drivers.
+
+===========================================================================
+max slew violation count 0
+max fanout violation count 14
+max cap violation count 0
+============================================================================
+
+===========================================================================
+check_setup -verbose -unconstrained_endpoints -multiple_clock -no_clock -no_input_delay -loops -generated_clocks
+===========================================================================
+Warning: There are 16 input ports missing set_input_delay.
+  io_in[0]
+  io_in[10]
+  io_in[11]
+  io_in[12]
+  io_in[13]
+  io_in[14]
+  io_in[15]
+  io_in[1]
+  io_in[2]
+  io_in[3]
+  io_in[4]
+  io_in[5]
+  io_in[6]
+  io_in[7]
+  io_in[8]
+  io_in[9]
+Warning: There are 163 unconstrained endpoints.
+  io_oeb[0]
+  io_oeb[10]
+  io_oeb[11]
+  io_oeb[12]
+  io_oeb[13]
+  io_oeb[14]
+  io_oeb[15]
+  io_oeb[1]
+  io_oeb[2]
+  io_oeb[3]
+  io_oeb[4]
+  io_oeb[5]
+  io_oeb[6]
+  io_oeb[7]
+  io_oeb[8]
+  io_oeb[9]
+  io_out[0]
+  io_out[10]
+  io_out[11]
+  io_out[12]
+  io_out[13]
+  io_out[14]
+  io_out[15]
+  io_out[1]
+  io_out[2]
+  io_out[3]
+  io_out[4]
+  io_out[5]
+  io_out[6]
+  io_out[7]
+  io_out[8]
+  io_out[9]
+  irq[0]
+  irq[1]
+  irq[2]
+  la_data_out[100]
+  la_data_out[101]
+  la_data_out[102]
+  la_data_out[103]
+  la_data_out[104]
+  la_data_out[105]
+  la_data_out[106]
+  la_data_out[107]
+  la_data_out[108]
+  la_data_out[109]
+  la_data_out[110]
+  la_data_out[111]
+  la_data_out[112]
+  la_data_out[113]
+  la_data_out[114]
+  la_data_out[115]
+  la_data_out[116]
+  la_data_out[117]
+  la_data_out[118]
+  la_data_out[119]
+  la_data_out[120]
+  la_data_out[121]
+  la_data_out[122]
+  la_data_out[123]
+  la_data_out[124]
+  la_data_out[125]
+  la_data_out[126]
+  la_data_out[127]
+  la_data_out[16]
+  la_data_out[17]
+  la_data_out[18]
+  la_data_out[19]
+  la_data_out[20]
+  la_data_out[21]
+  la_data_out[22]
+  la_data_out[23]
+  la_data_out[24]
+  la_data_out[25]
+  la_data_out[26]
+  la_data_out[27]
+  la_data_out[28]
+  la_data_out[29]
+  la_data_out[30]
+  la_data_out[31]
+  la_data_out[32]
+  la_data_out[33]
+  la_data_out[34]
+  la_data_out[35]
+  la_data_out[36]
+  la_data_out[37]
+  la_data_out[38]
+  la_data_out[39]
+  la_data_out[40]
+  la_data_out[41]
+  la_data_out[42]
+  la_data_out[43]
+  la_data_out[44]
+  la_data_out[45]
+  la_data_out[46]
+  la_data_out[47]
+  la_data_out[48]
+  la_data_out[49]
+  la_data_out[50]
+  la_data_out[51]
+  la_data_out[52]
+  la_data_out[53]
+  la_data_out[54]
+  la_data_out[55]
+  la_data_out[56]
+  la_data_out[57]
+  la_data_out[58]
+  la_data_out[59]
+  la_data_out[60]
+  la_data_out[61]
+  la_data_out[62]
+  la_data_out[63]
+  la_data_out[64]
+  la_data_out[65]
+  la_data_out[66]
+  la_data_out[67]
+  la_data_out[68]
+  la_data_out[69]
+  la_data_out[70]
+  la_data_out[71]
+  la_data_out[72]
+  la_data_out[73]
+  la_data_out[74]
+  la_data_out[75]
+  la_data_out[76]
+  la_data_out[77]
+  la_data_out[78]
+  la_data_out[79]
+  la_data_out[80]
+  la_data_out[81]
+  la_data_out[82]
+  la_data_out[83]
+  la_data_out[84]
+  la_data_out[85]
+  la_data_out[86]
+  la_data_out[87]
+  la_data_out[88]
+  la_data_out[89]
+  la_data_out[90]
+  la_data_out[91]
+  la_data_out[92]
+  la_data_out[93]
+  la_data_out[94]
+  la_data_out[95]
+  la_data_out[96]
+  la_data_out[97]
+  la_data_out[98]
+  la_data_out[99]
+  wbs_dat_o[16]
+  wbs_dat_o[17]
+  wbs_dat_o[18]
+  wbs_dat_o[19]
+  wbs_dat_o[20]
+  wbs_dat_o[21]
+  wbs_dat_o[22]
+  wbs_dat_o[23]
+  wbs_dat_o[24]
+  wbs_dat_o[25]
+  wbs_dat_o[26]
+  wbs_dat_o[27]
+  wbs_dat_o[28]
+  wbs_dat_o[29]
+  wbs_dat_o[30]
+  wbs_dat_o[31]

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/clock.rpt

@@ -0,0 +1,51 @@
+Clock: clk
+Sources: wb_clk_i 
+Generated: no
+Virtual: yes
+Propagated: no
+Period: 25.000000
+
+===========================================================================
+report_clock_properties
+============================================================================
+Clock                   Period          Waveform
+----------------------------------------------------
+clk                  25.000000    0.000000 12.500000
+
+===========================================================================
+report_clock_latency
+============================================================================
+Clock clk
+rise -> rise
+    min     max
+4.650000 5.570000 source latency
+5.793144         network latency _328_/CLK
+        8.802826 network latency _305_/CLK
+---------------
+10.443145 14.372827 latency
+        3.929682 skew
+
+rise -> fall
+    min     max
+4.650000 5.570000 source latency
+5.886471         network latency _328_/CLK
+        8.789217 network latency _305_/CLK
+---------------
+10.536470 14.359217 latency
+        3.822746 skew
+
+fall -> fall
+    min     max
+4.650000 5.570000 source latency
+5.926150         network latency _328_/CLK
+        6.861967 network latency _305_/CLK
+---------------
+10.576150 12.431967 latency
+        1.855817 skew
+
+
+
+===========================================================================
+report_clock_min_period
+============================================================================
+clk period_min = 3.67 fmax = 272.16

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/power.rpt

@@ -0,0 +1,18 @@
+
+===========================================================================
+ report_power
+============================================================================
+======================= max_ff_n40C_1v95 Corner ===================================
+
+Group                    Internal    Switching      Leakage        Total
+                            Power        Power        Power        Power (Watts)
+------------------------------------------------------------------------
+Sequential           4.245963e-05 4.360105e-05 7.394261e-10 8.606142e-05  13.8%
+Combinational        1.185844e-04 3.225572e-04 1.315145e-08 4.411547e-04  70.6%
+Clock                3.455588e-05 6.339366e-05 5.304953e-09 9.795484e-05  15.7%
+Macro                0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00   0.0%
+Pad                  0.000000e+00 0.000000e+00 0.000000e+00 0.000000e+00   0.0%
+------------------------------------------------------------------------
+Total                1.955999e-04 4.295520e-04 1.919599e-08 6.251711e-04 100.0%
+                            31.3%        68.7%         0.0%
+

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/skew.max.rpt

@@ -0,0 +1,14 @@
+
+===========================================================================
+Clock Skew (Setup)
+============================================================================
+======================= max_ff_n40C_1v95 Corner ===================================
+
+Clock clk
+8.802711 source latency _296_/CLK ^
+-5.793144 target latency _328_/CLK ^
+0.250000 clock uncertainty
+0.000000 CRPR
+--------------
+3.259567 setup skew
+

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/skew.min.rpt

@@ -0,0 +1,14 @@
+
+===========================================================================
+Clock Skew (Hold)
+============================================================================
+======================= max_ff_n40C_1v95 Corner ===================================
+
+Clock clk
+5.796201 source latency _306_/CLK ^
+-6.727007 target latency _312_/CLK ^
+-0.250000 clock uncertainty
+-0.920002 CRPR
+--------------
+-2.100808 hold skew
+

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/tns.max.rpt

@@ -0,0 +1,5 @@
+
+===========================================================================
+Total Negative Slack (Setup)
+============================================================================
+max_ff_n40C_1v95: 0.0

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/tns.min.rpt

@@ -0,0 +1,5 @@
+
+===========================================================================
+Total Negative Slack (Hold)
+============================================================================
+max_ff_n40C_1v95: 0.0

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/violator_list.rpt

@@ -0,0 +1,4 @@
+
+===========================================================================
+Violator List
+============================================================================

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/wns.max.rpt

@@ -0,0 +1,5 @@
+
+===========================================================================
+Worst Negative Slack (Setup)
+============================================================================
+max_ff_n40C_1v95: 0.0

signoff/user_proj_example/openlane-signoff/timing-reports/max_ff_n40C_1v95/wns.min.rpt

@@ -0,0 +1,5 @@
+
+===========================================================================
+Worst Negative Slack (Hold)
+============================================================================
+max_ff_n40C_1v95: 0