feat: integrate LDPC decoder into Caravel wrapper

- Copy ldpc_decoder_core.sv and wishbone_interface.sv from standalone RTL
- Create Caravel-adapted ldpc_decoder_top.sv with USE_POWER_PINS,
  32-bit address (lower 8 bits passed through), and wb_sel_i port
- Replace user_proj_example in user_project_wrapper.v with LDPC decoder
  instantiation, active-high to active-low reset inversion, and tie-offs
  for unused outputs (la_data_out, io_out, io_oeb, user_irq[2:1])
- Update includes.rtl.caravel_user_project with LDPC RTL file list
- Fix invalid hex literal in VERSION_ID (0xLD -> 0x1D)

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

verilog/rtl/user_project_wrapper.v

@@ -82,42 +82,30 @@ module user_project_wrapper #(
 /* User project is instantiated  here   */
 /*--------------------------------------*/
 
-user_proj_example mprj (
+ldpc_decoder_top mprj (
 `ifdef USE_POWER_PINS
-	.vccd1(vccd1),	// User area 1 1.8V power
-	.vssd1(vssd1),	// User area 1 digital ground
+    .vccd1(vccd1),
+    .vssd1(vssd1),
 `endif
-
-    .wb_clk_i(wb_clk_i),
-    .wb_rst_i(wb_rst_i),
-
-    // MGMT SoC Wishbone Slave
-
-    .wbs_cyc_i(wbs_cyc_i),
-    .wbs_stb_i(wbs_stb_i),
-    .wbs_we_i(wbs_we_i),
-    .wbs_sel_i(wbs_sel_i),
-    .wbs_adr_i(wbs_adr_i),
-    .wbs_dat_i(wbs_dat_i),
-    .wbs_ack_o(wbs_ack_o),
-    .wbs_dat_o(wbs_dat_o),
-
-    // Logic Analyzer
-
-    .la_data_in(la_data_in),
-    .la_data_out(la_data_out),
-    .la_oenb (la_oenb),
-
-    // IO Pads
-
-    .io_in ({io_in[37:30],io_in[7:0]}),
-    .io_out({io_out[37:30],io_out[7:0]}),
-    .io_oeb({io_oeb[37:30],io_oeb[7:0]}),
-
-    // IRQ
-    .irq(user_irq)
+    .clk        (wb_clk_i),
+    .rst_n      (~wb_rst_i),
+    .wb_cyc_i   (wbs_cyc_i),
+    .wb_stb_i   (wbs_stb_i),
+    .wb_we_i    (wbs_we_i),
+    .wb_sel_i   (wbs_sel_i),
+    .wb_adr_i   (wbs_adr_i),
+    .wb_dat_i   (wbs_dat_i),
+    .wb_dat_o   (wbs_dat_o),
+    .wb_ack_o   (wbs_ack_o),
+    .irq_o      (user_irq[0])
 );
 
+// Tie off unused outputs
+assign la_data_out = 128'b0;
+assign io_out = {`MPRJ_IO_PADS{1'b0}};
+assign io_oeb = {`MPRJ_IO_PADS{1'b1}};  // all inputs
+assign user_irq[2:1] = 2'b0;
+
 endmodule	// user_project_wrapper
 
 `default_nettype wire