feat: add OpenLane hardening config for LDPC decoder (50 MHz)

- config.json: 20ns clock period, AREA 2 synth strategy, 2800x1760um die
- pin_order.cfg: Wishbone pins on south, outputs on north
- base_ldpc.sdc: Caravel-calibrated timing constraints adapted for LDPC ports
- Updated wrapper config to reference ldpc_decoder_top macro

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
cah
2026-02-25 20:08:39 -07:00
parent 412c51a632
commit 81cffda1cb
4 changed files with 209 additions and 8 deletions

View File

@@ -0,0 +1,69 @@
{
"DESIGN_NAME": "ldpc_decoder_top",
"FP_PDN_MULTILAYER": false,
"VERILOG_FILES": [
"dir::../../verilog/rtl/defines.v",
"dir::../../verilog/rtl/ldpc_decoder_top.sv",
"dir::../../verilog/rtl/ldpc_decoder_core.sv",
"dir::../../verilog/rtl/wishbone_interface.sv"
],
"CLOCK_PERIOD": 20,
"CLOCK_PORT": "clk",
"CLOCK_NET": "u_core.clk",
"FP_SIZING": "absolute",
"DIE_AREA": [
0,
0,
2800,
1760
],
"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
"MAX_TRANSITION_CONSTRAINT": 1.5,
"MAX_FANOUT_CONSTRAINT": 16,
"PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
"GRT_RESIZER_SETUP_SLACK_MARGIN": 0.2,
"GRT_RESIZER_HOLD_SLACK_MARGIN": 0.2,
"PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
"CTS_CLK_MAX_WIRE_LENGTH": 500,
"MAGIC_DEF_LABELS": false,
"SYNTH_ABC_BUFFERING": false,
"RUN_HEURISTIC_DIODE_INSERTION": true,
"HEURISTIC_ANTENNA_THRESHOLD": 110,
"RUN_ANTENNA_REPAIR": true,
"RUN_POST_GRT_DESIGN_REPAIR": true,
"RUN_POST_GRT_RESIZER_TIMING": true,
"VDD_NETS": [
"vccd1"
],
"GND_NETS": [
"vssd1"
],
"FALLBACK_SDC_FILE": "dir::base_ldpc.sdc",
"MAGIC_DRC_USE_GDS": true,
"DPL_CELL_PADDING": 2,
"GPL_CELL_PADDING": 2,
"SYNTH_STRATEGY": "AREA 2",
"PL_TARGET_DENSITY_PCT": 40,
"pdk::sky130*": {
"RT_MAX_LAYER": "met4",
"scl::sky130_fd_sc_hd": {
"CLOCK_PERIOD": 20
},
"scl::sky130_fd_sc_hdll": {
"CLOCK_PERIOD": 10
},
"scl::sky130_fd_sc_hs": {
"CLOCK_PERIOD": 8
},
"scl::sky130_fd_sc_ls": {
"CLOCK_PERIOD": 10,
"SYNTH_MAX_FANOUT": 5
},
"scl::sky130_fd_sc_ms": {
"CLOCK_PERIOD": 10
}
},
"meta": {
"version": 2
}
}