feat: add OpenLane hardening config for LDPC decoder (50 MHz)

- config.json: 20ns clock period, AREA 2 synth strategy, 2800x1760um die
- pin_order.cfg: Wishbone pins on south, outputs on north
- base_ldpc.sdc: Caravel-calibrated timing constraints adapted for LDPC ports
- Updated wrapper config to reference ldpc_decoder_top macro

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

openlane/ldpc_decoder_top/pin_order.cfg

@@ -0,0 +1,16 @@
+#BUS_SORT
+
+#S
+clk
+rst_n
+wb_cyc_i
+wb_stb_i
+wb_we_i
+wb_sel_i\[.*\]
+wb_adr_i\[.*\]
+wb_dat_i\[.*\]
+
+#N
+wb_dat_o\[.*\]
+wb_ack_o
+irq_o