feat: add OpenLane hardening config for LDPC decoder (50 MHz)
- config.json: 20ns clock period, AREA 2 synth strategy, 2800x1760um die - pin_order.cfg: Wishbone pins on south, outputs on north - base_ldpc.sdc: Caravel-calibrated timing constraints adapted for LDPC ports - Updated wrapper config to reference ldpc_decoder_top macro Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
116
openlane/ldpc_decoder_top/base_ldpc.sdc
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116
openlane/ldpc_decoder_top/base_ldpc.sdc
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# SDC constraints for ldpc_decoder_top
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# Adapted from Caravel user_proj_example SDC
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# Target: 50 MHz (20 ns period)
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### Note:
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# - input clock transition and latency are set for clk port.
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# - IO ports are assumed to be asynchronous (IO_SYNC=0).
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#------------------------------------------#
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# Pre-defined Constraints
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#------------------------------------------#
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set ::env(IO_SYNC) 0
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# Clock network
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if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
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set clk_input $::env(CLOCK_PORT)
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create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
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puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
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} else {
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set clk_input __VIRTUAL_CLK__
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create_clock -name clk -period $::env(CLOCK_PERIOD)
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puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
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}
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if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
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set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
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}
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if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
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set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
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}
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# Clock non-idealities
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set_propagated_clock [all_clocks]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
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puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
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puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
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# Maximum transition time for the design nets
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set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
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puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
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# Maximum fanout
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set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
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puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
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# Timing paths delays derate
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set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
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set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
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puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
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# Reset input delay
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set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {rst_n}]
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# Multicycle paths for Wishbone handshake
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set_multicycle_path -setup 2 -through [get_ports {wb_ack_o}]
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set_multicycle_path -hold 1 -through [get_ports {wb_ack_o}]
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set_multicycle_path -setup 2 -through [get_ports {wb_cyc_i}]
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set_multicycle_path -hold 1 -through [get_ports {wb_cyc_i}]
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set_multicycle_path -setup 2 -through [get_ports {wb_stb_i}]
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set_multicycle_path -hold 1 -through [get_ports {wb_stb_i}]
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#------------------------------------------#
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# Retrieved Constraints (from Caravel)
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#------------------------------------------#
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# Clock source latency
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set clk_max_latency 5.57
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set clk_min_latency 4.65
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set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
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set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
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puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
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# Clock input Transition
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set clk_tran 0.61
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set_input_transition $clk_tran [get_ports $clk_input]
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puts "\[INFO\]: Setting clock transition: $clk_tran"
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# Input delays (scaled from Caravel characterization)
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set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wb_sel_i[*]}]
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set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wb_we_i}]
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set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wb_adr_i[*]}]
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set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wb_stb_i}]
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set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wb_dat_i[*]}]
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set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wb_cyc_i}]
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set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wb_adr_i[*]}]
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set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wb_dat_i[*]}]
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set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wb_sel_i[*]}]
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set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wb_we_i}]
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set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wb_cyc_i}]
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set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wb_stb_i}]
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# Input Transition
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set_input_transition -max 0.14 [get_ports {wb_we_i}]
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set_input_transition -max 0.15 [get_ports {wb_stb_i}]
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set_input_transition -max 0.17 [get_ports {wb_cyc_i}]
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set_input_transition -max 0.18 [get_ports {wb_sel_i[*]}]
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set_input_transition -max 0.84 [get_ports {wb_dat_i[*]}]
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set_input_transition -max 0.92 [get_ports {wb_adr_i[*]}]
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set_input_transition -min 0.07 [get_ports {wb_adr_i[*]}]
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set_input_transition -min 0.07 [get_ports {wb_dat_i[*]}]
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set_input_transition -min 0.09 [get_ports {wb_cyc_i}]
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set_input_transition -min 0.09 [get_ports {wb_sel_i[*]}]
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set_input_transition -min 0.09 [get_ports {wb_we_i}]
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set_input_transition -min 0.15 [get_ports {wb_stb_i}]
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# Output delays
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set_output_delay -max 0.7 -clock [get_clocks {clk}] [get_ports {irq_o}]
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set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wb_dat_o[*]}]
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set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wb_ack_o}]
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set_output_delay -min 0 -clock [get_clocks {clk}] [get_ports {irq_o}]
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set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wb_dat_o[*]}]
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set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wb_ack_o}]
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# Output loads
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set_load 0.19 [all_outputs]
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69
openlane/ldpc_decoder_top/config.json
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69
openlane/ldpc_decoder_top/config.json
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@@ -0,0 +1,69 @@
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{
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"DESIGN_NAME": "ldpc_decoder_top",
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"FP_PDN_MULTILAYER": false,
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"VERILOG_FILES": [
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"dir::../../verilog/rtl/defines.v",
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"dir::../../verilog/rtl/ldpc_decoder_top.sv",
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"dir::../../verilog/rtl/ldpc_decoder_core.sv",
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"dir::../../verilog/rtl/wishbone_interface.sv"
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],
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"CLOCK_PERIOD": 20,
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"CLOCK_PORT": "clk",
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"CLOCK_NET": "u_core.clk",
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"FP_SIZING": "absolute",
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"DIE_AREA": [
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0,
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0,
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2800,
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1760
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],
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"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
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"MAX_TRANSITION_CONSTRAINT": 1.5,
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"MAX_FANOUT_CONSTRAINT": 16,
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"PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
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"GRT_RESIZER_SETUP_SLACK_MARGIN": 0.2,
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"GRT_RESIZER_HOLD_SLACK_MARGIN": 0.2,
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"PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
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"CTS_CLK_MAX_WIRE_LENGTH": 500,
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"MAGIC_DEF_LABELS": false,
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"SYNTH_ABC_BUFFERING": false,
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"RUN_HEURISTIC_DIODE_INSERTION": true,
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"HEURISTIC_ANTENNA_THRESHOLD": 110,
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"RUN_ANTENNA_REPAIR": true,
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"RUN_POST_GRT_DESIGN_REPAIR": true,
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"RUN_POST_GRT_RESIZER_TIMING": true,
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"VDD_NETS": [
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"vccd1"
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],
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"GND_NETS": [
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"vssd1"
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],
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"FALLBACK_SDC_FILE": "dir::base_ldpc.sdc",
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"MAGIC_DRC_USE_GDS": true,
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"DPL_CELL_PADDING": 2,
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"GPL_CELL_PADDING": 2,
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"SYNTH_STRATEGY": "AREA 2",
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"PL_TARGET_DENSITY_PCT": 40,
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"pdk::sky130*": {
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"RT_MAX_LAYER": "met4",
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"scl::sky130_fd_sc_hd": {
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"CLOCK_PERIOD": 20
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},
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"scl::sky130_fd_sc_hdll": {
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"CLOCK_PERIOD": 10
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},
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"scl::sky130_fd_sc_hs": {
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"CLOCK_PERIOD": 8
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},
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"scl::sky130_fd_sc_ls": {
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"CLOCK_PERIOD": 10,
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"SYNTH_MAX_FANOUT": 5
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},
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"scl::sky130_fd_sc_ms": {
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"CLOCK_PERIOD": 10
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}
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},
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"meta": {
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"version": 2
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}
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}
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16
openlane/ldpc_decoder_top/pin_order.cfg
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16
openlane/ldpc_decoder_top/pin_order.cfg
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@@ -0,0 +1,16 @@
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#BUS_SORT
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#S
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clk
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rst_n
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wb_cyc_i
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wb_stb_i
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wb_we_i
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wb_sel_i\[.*\]
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wb_adr_i\[.*\]
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wb_dat_i\[.*\]
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#N
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wb_dat_o\[.*\]
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wb_ack_o
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irq_o
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@@ -21,12 +21,12 @@
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"//": "Macros configurations",
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"MACROS": {
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"user_proj_example": {
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"ldpc_decoder_top": {
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"gds": [
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"dir::../../gds/user_proj_example.gds"
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"dir::../../gds/ldpc_decoder_top.gds"
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],
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"lef": [
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"dir::../../lef/user_proj_example.lef"
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"dir::../../lef/ldpc_decoder_top.lef"
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],
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"instances": {
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"mprj": {
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@@ -35,21 +35,21 @@
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}
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},
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"nl": [
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"dir::../../verilog/gl/user_proj_example.v"
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"dir::../../verilog/gl/ldpc_decoder_top.v"
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],
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"spef": {
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"min_*": [
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"dir::../../spef/multicorner/user_proj_example.min.spef"
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"dir::../../spef/multicorner/ldpc_decoder_top.min.spef"
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],
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"nom_*": [
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"dir::../../spef/multicorner/user_proj_example.nom.spef"
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"dir::../../spef/multicorner/ldpc_decoder_top.nom.spef"
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],
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"max_*": [
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"dir::../../spef/multicorner/user_proj_example.max.spef"
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"dir::../../spef/multicorner/ldpc_decoder_top.max.spef"
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]
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},
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"lib": {
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"*": "dir::../../lib/user_proj_example.lib"
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"*": "dir::../../lib/ldpc_decoder_top.lib"
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}
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}
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},
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