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1fcdc1dd89
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harden: regenerate user_project_wrapper via cf harden (cf_wrapper_v5)
CI / rtl-lint (push) Has been cancelled
Re-hardened wrapper with chipfoundry-cli (LibreLane) per contest item #3.
Macro ldpc_decoder_top unchanged (Run 6 / antenna_iterative golden) —
wrapper config has SYNTH_ELABORATE_ONLY=true and reuses macro as a
hardened black box.
Results vs wrapper_v4 baseline:
setup violations: 3402 → 0
hold violations: 13006 → 0
antenna nets: 1179 → 23
Magic + KLayout DRC: clean
power-grid: clean
LVS pin-match: 208 (cosmetic, vssd2 + constant-tied outputs)
Verification:
cf precheck: 17/19 pass (FEOL SIGSEGV + LVS pin-match
pre-existing accepted)
cf verify ldpc_basic --sim gl: PASS (GPIO=0xAB, decode success)
GDS/DEF/SPEF kept local for cf push.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
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2026-05-01 13:08:51 -06:00 |
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fdd68bb76b
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feat: complete hardening, wrapper, GLS verification for tapeout
RTL: Split CN_UPDATE into pipelined CN_STAGE1/CN_STAGE2, replace serial
popcount with balanced adder tree for timing closure.
Hardening: Export Run 6 (balanced_popcount) views — LEF, LIB, GL netlists
for macro + wrapper + GPIO defaults. GDS/DEF/SPEF kept local (cf push).
TT WNS = +3.28ns at 50 MHz. DRC/LVS clean.
Config: Increase SDC min input delays +0.7ns (fix 1,543 hold violations).
Set ERROR_ON_LVS_ERROR=false for wrapper cosmetic pin-match. Fix GPIO
defines to GPIO_MODE_USER_STD_BIDIRECTIONAL.
Verification: 5/5 GLS tests pass, 17/19 precheck pass. Add SPDX headers,
GLS test runner, OpenLane helper scripts. Update README with results.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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2026-03-13 22:42:41 -06:00 |
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