Metric,Value
design__lint_error__count,0
design__lint_timing_construct__count,0
design__lint_warning__count,5
design__inferred_latch__count,0
design__instance__count,1
design__instance_unmapped__count,0
synthesis__check_error__count,0
design__max_slew_violation__count__corner:nom_tt_025C_1v80,0
design__max_fanout_violation__count__corner:nom_tt_025C_1v80,31
design__max_cap_violation__count__corner:nom_tt_025C_1v80,0
power__internal__total,0.00019575921760406345
power__switching__total,0.00044556421926245093
power__leakage__total,1.919598524580124E-8
power__total,0.0006413426599465311
clock__skew__worst_hold__corner:nom_tt_025C_1v80,-2.096730848291461
clock__skew__worst_setup__corner:nom_tt_025C_1v80,3.153387418219582
timing__hold__ws__corner:nom_tt_025C_1v80,0.3479669983976151
timing__setup__ws__corner:nom_tt_025C_1v80,7.060524809099921
timing__hold__tns__corner:nom_tt_025C_1v80,0.0
timing__setup__tns__corner:nom_tt_025C_1v80,0.0
timing__hold__wns__corner:nom_tt_025C_1v80,0
timing__setup__wns__corner:nom_tt_025C_1v80,0.0
timing__hold_vio__count__corner:nom_tt_025C_1v80,0
timing__hold_r2r__ws__corner:nom_tt_025C_1v80,1.019479
timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_vio__count__corner:nom_tt_025C_1v80,0
timing__setup_r2r__ws__corner:nom_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80,0
design__max_slew_violation__count__corner:nom_ss_100C_1v60,4
design__max_fanout_violation__count__corner:nom_ss_100C_1v60,31
design__max_cap_violation__count__corner:nom_ss_100C_1v60,1
clock__skew__worst_hold__corner:nom_ss_100C_1v60,-2.0973783303777345
clock__skew__worst_setup__corner:nom_ss_100C_1v60,3.0065613072387984
timing__hold__ws__corner:nom_ss_100C_1v60,1.0254970496377398
timing__setup__ws__corner:nom_ss_100C_1v60,2.424894131904935
timing__hold__tns__corner:nom_ss_100C_1v60,0.0
timing__setup__tns__corner:nom_ss_100C_1v60,0.0
timing__hold__wns__corner:nom_ss_100C_1v60,0
timing__setup__wns__corner:nom_ss_100C_1v60,0.0
timing__hold_vio__count__corner:nom_ss_100C_1v60,0
timing__hold_r2r__ws__corner:nom_ss_100C_1v60,2.235596
timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_vio__count__corner:nom_ss_100C_1v60,0
timing__setup_r2r__ws__corner:nom_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60,0
design__max_slew_violation__count__corner:nom_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:nom_ff_n40C_1v95,31
design__max_cap_violation__count__corner:nom_ff_n40C_1v95,0
clock__skew__worst_hold__corner:nom_ff_n40C_1v95,-2.0964635065795703
clock__skew__worst_setup__corner:nom_ff_n40C_1v95,3.2516608104250833
timing__hold__ws__corner:nom_ff_n40C_1v95,0.2570081997744249
timing__setup__ws__corner:nom_ff_n40C_1v95,8.432016212809332
timing__hold__tns__corner:nom_ff_n40C_1v95,0.0
timing__setup__tns__corner:nom_ff_n40C_1v95,0.0
timing__hold__wns__corner:nom_ff_n40C_1v95,0
timing__setup__wns__corner:nom_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:nom_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:nom_ff_n40C_1v95,0.587006
timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_vio__count__corner:nom_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:nom_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95,0
design__max_slew_violation__count__corner:min_tt_025C_1v80,0
design__max_fanout_violation__count__corner:min_tt_025C_1v80,31
design__max_cap_violation__count__corner:min_tt_025C_1v80,0
clock__skew__worst_hold__corner:min_tt_025C_1v80,-2.0946271976449062
clock__skew__worst_setup__corner:min_tt_025C_1v80,3.1658698780830754
timing__hold__ws__corner:min_tt_025C_1v80,0.4135385484433063
timing__setup__ws__corner:min_tt_025C_1v80,7.08808853895645
timing__hold__tns__corner:min_tt_025C_1v80,0.0
timing__setup__tns__corner:min_tt_025C_1v80,0.0
timing__hold__wns__corner:min_tt_025C_1v80,0
timing__setup__wns__corner:min_tt_025C_1v80,0.0
timing__hold_vio__count__corner:min_tt_025C_1v80,0
timing__hold_r2r__ws__corner:min_tt_025C_1v80,0.992008
timing__hold_r2r_vio__count__corner:min_tt_025C_1v80,0
timing__setup_vio__count__corner:min_tt_025C_1v80,0
timing__setup_r2r__ws__corner:min_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:min_tt_025C_1v80,0
design__max_slew_violation__count__corner:min_ss_100C_1v60,0
design__max_fanout_violation__count__corner:min_ss_100C_1v60,31
design__max_cap_violation__count__corner:min_ss_100C_1v60,0
clock__skew__worst_hold__corner:min_ss_100C_1v60,-2.0952484784670573
clock__skew__worst_setup__corner:min_ss_100C_1v60,3.035826786995602
timing__hold__ws__corner:min_ss_100C_1v60,1.14169033014592
timing__setup__ws__corner:min_ss_100C_1v60,2.495028254621664
timing__hold__tns__corner:min_ss_100C_1v60,0.0
timing__setup__tns__corner:min_ss_100C_1v60,0.0
timing__hold__wns__corner:min_ss_100C_1v60,0
timing__setup__wns__corner:min_ss_100C_1v60,0.0
timing__hold_vio__count__corner:min_ss_100C_1v60,0
timing__hold_r2r__ws__corner:min_ss_100C_1v60,2.180078
timing__hold_r2r_vio__count__corner:min_ss_100C_1v60,0
timing__setup_vio__count__corner:min_ss_100C_1v60,0
timing__setup_r2r__ws__corner:min_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:min_ss_100C_1v60,0
design__max_slew_violation__count__corner:min_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:min_ff_n40C_1v95,31
design__max_cap_violation__count__corner:min_ff_n40C_1v95,0
clock__skew__worst_hold__corner:min_ff_n40C_1v95,-2.094480648201511
clock__skew__worst_setup__corner:min_ff_n40C_1v95,3.2563974660713058
timing__hold__ws__corner:min_ff_n40C_1v95,0.3004605538303306
timing__setup__ws__corner:min_ff_n40C_1v95,8.453748162997176
timing__hold__tns__corner:min_ff_n40C_1v95,0.0
timing__setup__tns__corner:min_ff_n40C_1v95,0.0
timing__hold__wns__corner:min_ff_n40C_1v95,0
timing__setup__wns__corner:min_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:min_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:min_ff_n40C_1v95,0.571340
timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_vio__count__corner:min_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:min_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95,0
design__max_slew_violation__count__corner:max_tt_025C_1v80,0
design__max_fanout_violation__count__corner:max_tt_025C_1v80,31
design__max_cap_violation__count__corner:max_tt_025C_1v80,0
clock__skew__worst_hold__corner:max_tt_025C_1v80,-2.1012276957575824
clock__skew__worst_setup__corner:max_tt_025C_1v80,3.1584722398161738
timing__hold__ws__corner:max_tt_025C_1v80,0.33149040006776803
timing__setup__ws__corner:max_tt_025C_1v80,7.0531102954425675
timing__hold__tns__corner:max_tt_025C_1v80,0.0
timing__setup__tns__corner:max_tt_025C_1v80,0.0
timing__hold__wns__corner:max_tt_025C_1v80,0
timing__setup__wns__corner:max_tt_025C_1v80,0.0
timing__hold_vio__count__corner:max_tt_025C_1v80,0
timing__hold_r2r__ws__corner:max_tt_025C_1v80,1.026777
timing__hold_r2r_vio__count__corner:max_tt_025C_1v80,0
timing__setup_vio__count__corner:max_tt_025C_1v80,0
timing__setup_r2r__ws__corner:max_tt_025C_1v80,Infinity
timing__setup_r2r_vio__count__corner:max_tt_025C_1v80,0
design__max_slew_violation__count__corner:max_ss_100C_1v60,4
design__max_fanout_violation__count__corner:max_ss_100C_1v60,31
design__max_cap_violation__count__corner:max_ss_100C_1v60,1
clock__skew__worst_hold__corner:max_ss_100C_1v60,-2.101982647435679
clock__skew__worst_setup__corner:max_ss_100C_1v60,3.004768963137153
timing__hold__ws__corner:max_ss_100C_1v60,0.9999921174163022
timing__setup__ws__corner:max_ss_100C_1v60,2.393246557559126
timing__hold__tns__corner:max_ss_100C_1v60,0.0
timing__setup__tns__corner:max_ss_100C_1v60,0.0
timing__hold__wns__corner:max_ss_100C_1v60,0
timing__setup__wns__corner:max_ss_100C_1v60,0.0
timing__hold_vio__count__corner:max_ss_100C_1v60,0
timing__hold_r2r__ws__corner:max_ss_100C_1v60,2.250683
timing__hold_r2r_vio__count__corner:max_ss_100C_1v60,0
timing__setup_vio__count__corner:max_ss_100C_1v60,0
timing__setup_r2r__ws__corner:max_ss_100C_1v60,Infinity
timing__setup_r2r_vio__count__corner:max_ss_100C_1v60,0
design__max_slew_violation__count__corner:max_ff_n40C_1v95,0
design__max_fanout_violation__count__corner:max_ff_n40C_1v95,31
design__max_cap_violation__count__corner:max_ff_n40C_1v95,0
clock__skew__worst_hold__corner:max_ff_n40C_1v95,-2.1008075873531826
clock__skew__worst_setup__corner:max_ff_n40C_1v95,3.258114315005142
timing__hold__ws__corner:max_ff_n40C_1v95,0.243695293065025
timing__setup__ws__corner:max_ff_n40C_1v95,8.420965496598887
timing__hold__tns__corner:max_ff_n40C_1v95,0.0
timing__setup__tns__corner:max_ff_n40C_1v95,0.0
timing__hold__wns__corner:max_ff_n40C_1v95,0
timing__setup__wns__corner:max_ff_n40C_1v95,0.0
timing__hold_vio__count__corner:max_ff_n40C_1v95,0
timing__hold_r2r__ws__corner:max_ff_n40C_1v95,0.591791
timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_vio__count__corner:max_ff_n40C_1v95,0
timing__setup_r2r__ws__corner:max_ff_n40C_1v95,Infinity
timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95,0
design__max_slew_violation__count,4
design__max_fanout_violation__count,31
design__max_cap_violation__count,1
clock__skew__worst_hold,-2.094480648201511
clock__skew__worst_setup,3.004768963137153
timing__hold__ws,0.243695293065025
timing__setup__ws,2.393246557559126
timing__hold__tns,0.0
timing__setup__tns,0.0
timing__hold__wns,0
timing__setup__wns,0.0
timing__hold_vio__count,0
timing__hold_r2r__ws,0.571340
timing__hold_r2r_vio__count,0
timing__setup_vio__count,0
timing__setup_r2r__ws,inf
timing__setup_r2r_vio__count,0
design__die__bbox,0.0 0.0 2920.0 3520.0
design__core__bbox,5.52 10.88 2914.1 3508.8
design__io,645
design__die__area,1.02784E+7
design__core__area,1.0174E+7
design__instance__area,4.928E+6
design__instance__count__stdcell,0
design__instance__area__stdcell,0
design__instance__count__macros,1
design__instance__area__macros,4.928E+6
design__instance__utilization,0.484373
design__instance__utilization__stdcell,0
design__instance__count__class:macro,1
flow__warnings__count,1
flow__errors__count,0
design__power_grid_violation__count__net:vccd1,0
design__power_grid_violation__count__net:vdda2,0
design__power_grid_violation__count__net:vdda1,0
design__power_grid_violation__count__net:vssd1,0
design__power_grid_violation__count__net:vssa2,0
design__power_grid_violation__count__net:vssa1,0
design__power_grid_violation__count__net:vssd2,0
design__power_grid_violation__count__net:vccd2,0
design__power_grid_violation__count,0
design__instance__displacement__total,0
design__instance__displacement__mean,0
design__instance__displacement__max,0
route__wirelength__estimated,39520
design__violations,0
antenna__violating__nets,0
antenna__violating__pins,0
route__antenna_violation__count,0
route__net,637
route__net__special,8
route__drc_errors__iter:1,142
route__wirelength__iter:1,37510
route__drc_errors__iter:2,56
route__wirelength__iter:2,37561
route__drc_errors__iter:3,51
route__wirelength__iter:3,37560
route__drc_errors__iter:4,0
route__wirelength__iter:4,37549
route__drc_errors,0
route__wirelength,37549
route__vias,1198
route__vias__singlecut,1198
route__vias__multicut,0
design__disconnected_pin__count,102
design__critical_disconnected_pin__count,0
route__wirelength__max,206.14
timing__unannotated_net__count__corner:nom_tt_025C_1v80,186
timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80,0
timing__unannotated_net__count__corner:nom_ss_100C_1v60,186
timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60,0
timing__unannotated_net__count__corner:nom_ff_n40C_1v95,186
timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95,0
timing__unannotated_net__count__corner:min_tt_025C_1v80,186
timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80,0
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timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60,0
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timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95,0
timing__unannotated_net__count__corner:max_tt_025C_1v80,186
timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80,0
timing__unannotated_net__count__corner:max_ss_100C_1v60,186
timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60,0
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timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95,0
timing__unannotated_net__count,186
timing__unannotated_net_filtered__count,0
design__xor_difference__count,0
magic__drc_error__count,0
klayout__drc_error__count,0
magic__illegal_overlap__count,0
design__lvs_device_difference__count,0
design__lvs_net_difference__count,0
design__lvs_property_fail__count,0
design__lvs_error__count,0
design__lvs_unmatched_device__count,0
design__lvs_unmatched_net__count,0
design__lvs_unmatched_pin__count,0