cah
81cffda1cb
- config.json: 20ns clock period, AREA 2 synth strategy, 2800x1760um die - pin_order.cfg: Wishbone pins on south, outputs on north - base_ldpc.sdc: Caravel-calibrated timing constraints adapted for LDPC ports - Updated wrapper config to reference ldpc_decoder_top macro Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
17 lines
129 B
INI
17 lines
129 B
INI
#BUS_SORT
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#S
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clk
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rst_n
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wb_cyc_i
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wb_stb_i
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wb_we_i
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wb_sel_i\[.*\]
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wb_adr_i\[.*\]
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wb_dat_i\[.*\]
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#N
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wb_dat_o\[.*\]
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wb_ack_o
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irq_o
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