cah
5d615876ae
- Copy ldpc_decoder_core.sv and wishbone_interface.sv from standalone RTL - Create Caravel-adapted ldpc_decoder_top.sv with USE_POWER_PINS, 32-bit address (lower 8 bits passed through), and wb_sel_i port - Replace user_proj_example in user_project_wrapper.v with LDPC decoder instantiation, active-high to active-low reset inversion, and tie-offs for unused outputs (la_data_out, io_out, io_oeb, user_irq[2:1]) - Update includes.rtl.caravel_user_project with LDPC RTL file list - Fix invalid hex literal in VERSION_ID (0xLD -> 0x1D) Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
22 lines
921 B
Plaintext
22 lines
921 B
Plaintext
# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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# Caravel user project includes
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-v $(USER_PROJECT_VERILOG)/rtl/defines.v
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-v $(USER_PROJECT_VERILOG)/rtl/user_project_wrapper.v
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-v $(USER_PROJECT_VERILOG)/rtl/ldpc_decoder_top.sv
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-v $(USER_PROJECT_VERILOG)/rtl/ldpc_decoder_core.sv
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-v $(USER_PROJECT_VERILOG)/rtl/wishbone_interface.sv
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