28 lines
1.0 KiB
Verilog
28 lines
1.0 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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// Include caravel global defines for the number of the user project IO pads
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`include "defines.v"
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`define USE_POWER_PINS
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`ifdef GL
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// Assume default net type to be wire because GL netlists don't have the wire definitions
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`default_nettype wire
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`include "gl/user_project_wrapper.v"
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`include "gl/user_proj_example.v"
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`else
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`include "user_project_wrapper.v"
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`include "user_proj_example.v"
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`endif |