Files
chip_ignite/verilog/rtl
cah 412c51a632 fix: three RTL bugs found by vector-driven testbench
- Magnitude overflow for -32 in cn_min_sum (clamp to 31)
- Converged flag cleared prematurely in IDLE (move to INIT)
- msg_cn2vn zeroing race in first iteration (bypass old_msg read)

All 20 test vectors now pass bit-exact against Python model.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-25 19:55:42 -07:00
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2026-02-23 20:42:11 -07:00
2026-02-23 20:42:11 -07:00
2026-02-23 20:42:11 -07:00
2026-02-23 20:42:11 -07:00