136 lines
5.1 KiB
C
136 lines
5.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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*/
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// This include is relative to $CARAVEL_PATH (see Makefile)
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#include <defs.h>
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// --------------------------------------------------------
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void main()
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{
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// The upper GPIO pins are configured to be output
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// and accessble to the management SoC.
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// Used to flag the start/end of a test
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// The lower GPIO pins are configured to be output
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// and accessible to the user project. They show
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// the project count value, although this test is
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// designed to read the project count through the
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// logic analyzer probes.
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// I/O 6 is configured for the UART Tx line
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uint32_t testval;
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reg_mprj_datal = 0x00000000;
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reg_mprj_datah = 0x00000000;
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reg_mprj_io_37 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_36 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_15 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_14 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_13 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_12 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_11 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_10 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_9 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_8 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_7 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_6 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_5 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_4 = GPIO_MODE_USER_STD_OUT_MONITORED;
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// reg_mprj_io_3 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_2 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_1 = GPIO_MODE_USER_STD_OUT_MONITORED;
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reg_mprj_io_0 = GPIO_MODE_USER_STD_OUT_MONITORED;
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/* Apply configuration */
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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/* TEST: Recast channels 35 to 32 to allow input to user project */
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/* This is done locally only: Do not run reg_mprj_xfer! */
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reg_mprj_io_35 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_34 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_33 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_32 = GPIO_MODE_MGMT_STD_OUTPUT;
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// Configure LA probes [31:0], [127:64] as inputs to the cpu
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// Configure LA probes [63:32] as outputs from the cpu
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reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
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reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF; // [63:32]
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reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
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reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
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// Flag start of the test
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reg_mprj_datal = 0xAB400000;
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// Set Counter value to zero through LA probes [63:32]
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reg_la1_data = 0x00000000;
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// Configure LA probes from [63:32] as inputs to disable counter write
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reg_la1_oenb = reg_la1_iena = 0x00000000;
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reg_mprj_datal = 0xAB410000;
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reg_mprj_datah = 0x00000000;
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// Test ability to force data on channel 37
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// NOTE: Only the low 6 bits of reg_mprj_datah are meaningful
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reg_mprj_datah = 0x0f0f0fc0;
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reg_mprj_datah = 0x00000000;
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reg_mprj_datah = 0x0f0f0fca;
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reg_mprj_datah = 0x0000000a;
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reg_mprj_datah = 0x0f0f0fc0;
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reg_mprj_datah = 0x00000000;
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reg_mprj_datah = 0x0f0f0fc5;
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reg_mprj_datah = 0x00000005;
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// Test ability to read back data generated by the user project
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// on the "monitored" outputs. Read from the lower 16 bits and
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// copy the value to the upper 16 bits.
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testval = reg_mprj_datal;
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reg_mprj_datal = (testval << 16);
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reg_mprj_datah = 0x0000000a;
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testval = reg_mprj_datal;
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reg_mprj_datal = (testval << 16);
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reg_mprj_datah = 0x00000005;
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// Flag end of the test
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reg_mprj_datal = 0xAB510000;
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} |