cah
f2e419e25d
Yosys doesn't support unpacked array ports. Changed llr_in/llr_input from `logic signed [Q-1:0] llr[N]` to `logic [N*Q-1:0] llr` packed vector. Also fixed blocking assignment in INIT loops (Verilator BLKLOOPINIT requirement). Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
74 lines
2.7 KiB
Systemverilog
74 lines
2.7 KiB
Systemverilog
// LDPC Decoder Top - Caravel-adapted wrapper
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// QC-LDPC Rate 1/8 for Photon-Starved Optical Communication
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// Target: Efabless chipIgnite (SkyWater 130nm, Caravel harness)
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//
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// Adaptations from standalone version:
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// - USE_POWER_PINS ifdef for Caravel power pass-through
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// - 32-bit Wishbone address (lower 8 bits passed to wishbone_interface)
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// - wb_sel_i byte selects accepted but unused (word-aligned access only)
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// - LLR interface uses packed vector (Yosys compatibility)
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module ldpc_decoder_top #(
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parameter N_BASE = 8,
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parameter M_BASE = 7,
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parameter Z = 32,
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parameter N = N_BASE * Z,
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parameter K = Z,
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parameter Q = 6,
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parameter MAX_ITER = 30,
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parameter DC = 8,
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parameter DV_MAX = 7
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)(
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`ifdef USE_POWER_PINS
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inout vccd1,
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inout vssd1,
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`endif
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input logic clk,
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input logic rst_n,
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input logic wb_cyc_i,
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input logic wb_stb_i,
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input logic wb_we_i,
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input logic [3:0] wb_sel_i, // byte selects (unused, Caravel compat)
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input logic [31:0] wb_adr_i, // full 32-bit address from Caravel
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input logic [31:0] wb_dat_i,
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output logic [31:0] wb_dat_o,
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output logic wb_ack_o,
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output logic irq_o
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);
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// Internal signals
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logic ctrl_start;
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logic ctrl_early_term;
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logic [4:0] ctrl_max_iter;
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logic stat_busy;
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logic stat_converged;
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logic [4:0] stat_iter_used;
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logic [N*Q-1:0] llr_input_flat; // packed LLR vector
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logic [K-1:0] decoded_bits;
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logic [7:0] syndrome_weight;
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wishbone_interface #(.N(N), .K(K), .Q(Q)) u_wb (
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.clk(clk), .rst_n(rst_n),
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.wb_cyc_i(wb_cyc_i), .wb_stb_i(wb_stb_i), .wb_we_i(wb_we_i),
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.wb_adr_i(wb_adr_i[7:0]), // lower 8 bits only
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.wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o), .wb_ack_o(wb_ack_o),
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.ctrl_start(ctrl_start), .ctrl_early_term(ctrl_early_term),
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.ctrl_max_iter(ctrl_max_iter),
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.stat_busy(stat_busy), .stat_converged(stat_converged),
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.stat_iter_used(stat_iter_used),
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.llr_input(llr_input_flat), .decoded_bits(decoded_bits),
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.syndrome_weight(syndrome_weight), .irq_o(irq_o)
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);
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ldpc_decoder_core #(
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.N_BASE(N_BASE), .M_BASE(M_BASE), .Z(Z), .Q(Q),
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.MAX_ITER(MAX_ITER), .DC(DC), .DV_MAX(DV_MAX)
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) u_core (
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.clk(clk), .rst_n(rst_n),
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.start(ctrl_start), .early_term_en(ctrl_early_term),
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.max_iter(ctrl_max_iter), .llr_in(llr_input_flat),
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.busy(stat_busy), .converged(stat_converged),
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.iter_used(stat_iter_used), .decoded_bits(decoded_bits),
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.syndrome_weight(syndrome_weight)
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);
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endmodule
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