cah
fdd68bb76b
RTL: Split CN_UPDATE into pipelined CN_STAGE1/CN_STAGE2, replace serial popcount with balanced adder tree for timing closure. Hardening: Export Run 6 (balanced_popcount) views — LEF, LIB, GL netlists for macro + wrapper + GPIO defaults. GDS/DEF/SPEF kept local (cf push). TT WNS = +3.28ns at 50 MHz. DRC/LVS clean. Config: Increase SDC min input delays +0.7ns (fix 1,543 hold violations). Set ERROR_ON_LVS_ERROR=false for wrapper cosmetic pin-match. Fix GPIO defines to GPIO_MODE_USER_STD_BIDIRECTIONAL. Verification: 5/5 GLS tests pass, 17/19 precheck pass. Add SPDX headers, GLS test runner, OpenLane helper scripts. Update README with results. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
120 lines
3.4 KiB
Verilog
120 lines
3.4 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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*-------------------------------------------------------------
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*
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* user_project_wrapper
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*
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* This wrapper enumerates all of the pins available to the
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* user for the user project.
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*
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* An example user project is provided in this wrapper. The
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* example should be removed and replaced with the actual
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* user project.
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*
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*-------------------------------------------------------------
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*/
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module user_project_wrapper #(
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parameter BITS = 32
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) (
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`ifdef USE_POWER_PINS
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inout vdda1, // User area 1 3.3V supply
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inout vdda2, // User area 2 3.3V supply
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inout vssa1, // User area 1 analog ground
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inout vssa2, // User area 2 analog ground
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inout vccd1, // User area 1 1.8V supply
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inout vccd2, // User area 2 1.8v supply
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inout vssd1, // User area 1 digital ground
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inout vssd2, // User area 2 digital ground
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`endif
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oenb,
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// IOs
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input [`MPRJ_IO_PADS-1:0] io_in,
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output [`MPRJ_IO_PADS-1:0] io_out,
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output [`MPRJ_IO_PADS-1:0] io_oeb,
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// Analog (direct connection to GPIO pad---use with caution)
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// Note that analog I/O is not available on the 7 lowest-numbered
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// GPIO pads, and so the analog_io indexing is offset from the
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// GPIO indexing by 7 (also upper 2 GPIOs do not have analog_io).
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inout [`MPRJ_IO_PADS-10:0] analog_io,
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// Independent clock (on independent integer divider)
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input user_clock2,
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// User maskable interrupt signals
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output [2:0] user_irq
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);
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/*--------------------------------------*/
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/* User project is instantiated here */
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/*--------------------------------------*/
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// Invert active-high wb_rst_i to active-low rst_n
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// Power pins omitted — connected by physical power grid in layout
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wire rst_n_internal;
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sky130_fd_sc_hd__inv_2 rst_inv (
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.Y(rst_n_internal),
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.A(wb_rst_i)
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);
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ldpc_decoder_top mprj (
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`ifdef USE_POWER_PINS
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.vccd1(vccd1),
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.vssd1(vssd1),
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`endif
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.clk (wb_clk_i),
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.rst_n (rst_n_internal),
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.wb_cyc_i (wbs_cyc_i),
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.wb_stb_i (wbs_stb_i),
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.wb_we_i (wbs_we_i),
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.wb_sel_i (wbs_sel_i),
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.wb_adr_i (wbs_adr_i),
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.wb_dat_i (wbs_dat_i),
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.wb_dat_o (wbs_dat_o),
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.wb_ack_o (wbs_ack_o),
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.irq_o (user_irq[0])
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);
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// Tie off unused outputs
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assign la_data_out = 128'b0;
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assign io_out = {`MPRJ_IO_PADS{1'b0}};
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assign io_oeb = {`MPRJ_IO_PADS{1'b1}}; // all inputs
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assign user_irq[2:1] = 2'b0;
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endmodule // user_project_wrapper
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`default_nettype wire
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