cah
fdd68bb76b
RTL: Split CN_UPDATE into pipelined CN_STAGE1/CN_STAGE2, replace serial popcount with balanced adder tree for timing closure. Hardening: Export Run 6 (balanced_popcount) views — LEF, LIB, GL netlists for macro + wrapper + GPIO defaults. GDS/DEF/SPEF kept local (cf push). TT WNS = +3.28ns at 50 MHz. DRC/LVS clean. Config: Increase SDC min input delays +0.7ns (fix 1,543 hold violations). Set ERROR_ON_LVS_ERROR=false for wrapper cosmetic pin-match. Fix GPIO defines to GPIO_MODE_USER_STD_BIDIRECTIONAL. Verification: 5/5 GLS tests pass, 17/19 precheck pass. Add SPDX headers, GLS test runner, OpenLane helper scripts. Update README with results. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
119 lines
5.3 KiB
Tcl
119 lines
5.3 KiB
Tcl
# SDC constraints for ldpc_decoder_top
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# Adapted from Caravel user_proj_example SDC
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# Target: 50 MHz (20 ns period)
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### Note:
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# - input clock transition and latency are set for clk port.
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# - IO ports are assumed to be asynchronous (IO_SYNC=0).
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#------------------------------------------#
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# Pre-defined Constraints
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#------------------------------------------#
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set ::env(IO_SYNC) 0
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# Clock network
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if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
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set clk_input $::env(CLOCK_PORT)
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create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
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puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
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} else {
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set clk_input __VIRTUAL_CLK__
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create_clock -name clk -period $::env(CLOCK_PERIOD)
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puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
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}
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if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
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set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
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}
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if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
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set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
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}
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# Clock non-idealities
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set_propagated_clock [all_clocks]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
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puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
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puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
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# Maximum transition time for the design nets
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set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
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puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
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# Maximum fanout
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set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
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puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
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# Timing paths delays derate
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set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
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set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
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puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
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# Reset input delay
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set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {rst_n}]
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# Multicycle paths for Wishbone handshake
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set_multicycle_path -setup 2 -through [get_ports {wb_ack_o}]
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set_multicycle_path -hold 1 -through [get_ports {wb_ack_o}]
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set_multicycle_path -setup 2 -through [get_ports {wb_cyc_i}]
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set_multicycle_path -hold 1 -through [get_ports {wb_cyc_i}]
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set_multicycle_path -setup 2 -through [get_ports {wb_stb_i}]
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set_multicycle_path -hold 1 -through [get_ports {wb_stb_i}]
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#------------------------------------------#
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# Retrieved Constraints (from Caravel)
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#------------------------------------------#
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# Clock source latency
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set clk_max_latency 5.57
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set clk_min_latency 4.65
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set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
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set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
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puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
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# Clock input Transition
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set clk_tran 0.61
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set_input_transition $clk_tran [get_ports $clk_input]
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puts "\[INFO\]: Setting clock transition: $clk_tran"
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# Input delays (scaled from Caravel characterization)
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set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wb_sel_i[*]}]
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set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wb_we_i}]
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set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wb_adr_i[*]}]
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set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wb_stb_i}]
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set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wb_dat_i[*]}]
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set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wb_cyc_i}]
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# Min input delays increased by +0.7 ns to fix 1,543 hold violations on input ports
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# (worst was -0.62 ns; +0.7 ns provides margin)
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set_input_delay -min 1.49 -clock [get_clocks {clk}] [get_ports {wb_adr_i[*]}]
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set_input_delay -min 1.74 -clock [get_clocks {clk}] [get_ports {wb_dat_i[*]}]
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set_input_delay -min 1.89 -clock [get_clocks {clk}] [get_ports {wb_sel_i[*]}]
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set_input_delay -min 2.35 -clock [get_clocks {clk}] [get_ports {wb_we_i}]
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set_input_delay -min 2.39 -clock [get_clocks {clk}] [get_ports {wb_cyc_i}]
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set_input_delay -min 2.56 -clock [get_clocks {clk}] [get_ports {wb_stb_i}]
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# Input Transition
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set_input_transition -max 0.14 [get_ports {wb_we_i}]
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set_input_transition -max 0.15 [get_ports {wb_stb_i}]
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set_input_transition -max 0.17 [get_ports {wb_cyc_i}]
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set_input_transition -max 0.18 [get_ports {wb_sel_i[*]}]
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set_input_transition -max 0.84 [get_ports {wb_dat_i[*]}]
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set_input_transition -max 0.92 [get_ports {wb_adr_i[*]}]
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set_input_transition -min 0.07 [get_ports {wb_adr_i[*]}]
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set_input_transition -min 0.07 [get_ports {wb_dat_i[*]}]
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set_input_transition -min 0.09 [get_ports {wb_cyc_i}]
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set_input_transition -min 0.09 [get_ports {wb_sel_i[*]}]
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set_input_transition -min 0.09 [get_ports {wb_we_i}]
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set_input_transition -min 0.15 [get_ports {wb_stb_i}]
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# Output delays
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set_output_delay -max 0.7 -clock [get_clocks {clk}] [get_ports {irq_o}]
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set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wb_dat_o[*]}]
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set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wb_ack_o}]
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set_output_delay -min 0 -clock [get_clocks {clk}] [get_ports {irq_o}]
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set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wb_dat_o[*]}]
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set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wb_ack_o}]
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# Output loads
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set_load 0.19 [all_outputs]
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