Files
chip_ignite/verilog/dv/cocotb/cocotb_tests.py
cah fdd68bb76b feat: complete hardening, wrapper, GLS verification for tapeout
RTL: Split CN_UPDATE into pipelined CN_STAGE1/CN_STAGE2, replace serial
popcount with balanced adder tree for timing closure.

Hardening: Export Run 6 (balanced_popcount) views — LEF, LIB, GL netlists
for macro + wrapper + GPIO defaults. GDS/DEF/SPEF kept local (cf push).
TT WNS = +3.28ns at 50 MHz. DRC/LVS clean.

Config: Increase SDC min input delays +0.7ns (fix 1,543 hold violations).
Set ERROR_ON_LVS_ERROR=false for wrapper cosmetic pin-match. Fix GPIO
defines to GPIO_MODE_USER_STD_BIDIRECTIONAL.

Verification: 5/5 GLS tests pass, 17/19 precheck pass. Add SPDX headers,
GLS test runner, OpenLane helper scripts. Update README with results.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-03-13 22:42:41 -06:00

15 lines
814 B
Python

# SPDX-FileCopyrightText: 2026 Corey Hahn
# SPDX-License-Identifier: Apache-2.0
from hello_world.hello_world import hello_world
from hello_world_uart.hello_world_uart import hello_world_uart
from user_proj_tests.counter_wb.counter_wb import counter_wb
from user_proj_tests.counter_la.counter_la import counter_la
from user_proj_tests.counter_la_reset.counter_la_reset import counter_la_reset
from user_proj_tests.counter_la_clk.counter_la_clk import counter_la_clk
from gpio_test.gpio_test import gpio_test
from ldpc_tests.ldpc_basic.ldpc_basic import ldpc_basic
from ldpc_tests.ldpc_noisy.ldpc_noisy import ldpc_noisy
from ldpc_tests.ldpc_max_iter.ldpc_max_iter import ldpc_max_iter
from ldpc_tests.ldpc_back_to_back.ldpc_back_to_back import ldpc_back_to_back
from ldpc_tests.ldpc_demo.ldpc_demo import ldpc_demo