121 lines
4.0 KiB
C
121 lines
4.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2020 Efabless Corporation
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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* SPDX-License-Identifier: Apache-2.0
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*/
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// This include is relative to $CARAVEL_PATH (see Makefile)
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#include <defs.h>
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#include <stub.c>
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/*
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MPRJ LA Test:
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- Sets counter clk through LA[64]
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- Sets counter rst through LA[65]
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- Observes count value for five clk cycle through LA[31:0]
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*/
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int clk = 0;
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int i;
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void main()
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{
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/* Set up the housekeeping SPI to be connected internally so */
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/* that external pin changes don't affect it. */
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// reg_spimaster_config = 0xa002; // Enable, prescaler = 2,
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reg_spi_enable = 1;
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// connect to housekeeping SPI
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// Connect the housekeeping SPI to the SPI master
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// so that the CSB line is not left floating. This allows
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// all of the GPIO pins to be used for user functions.
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// All GPIO pins are configured to be output
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// Used to flad the start/end of a test
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reg_mprj_io_31 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_30 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_29 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_28 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_27 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_26 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_25 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_24 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_23 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_22 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_21 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_20 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_19 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_18 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_17 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_16 = GPIO_MODE_MGMT_STD_OUTPUT;
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reg_mprj_io_15 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_14 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_13 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_12 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_11 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_10 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_9 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_8 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_7 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_5 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_4 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_3 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_2 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_1 = GPIO_MODE_USER_STD_OUTPUT;
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reg_mprj_io_0 = GPIO_MODE_USER_STD_OUTPUT;
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/* Apply configuration */
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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// Configure All LA probes as inputs to the cpu
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reg_la0_oenb = reg_la0_iena = 0x00000000; // [31:0]
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reg_la1_oenb = reg_la1_iena = 0x00000000; // [63:32]
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reg_la2_oenb = reg_la2_iena = 0x00000000; // [95:64]
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reg_la3_oenb = reg_la3_iena = 0x00000000; // [127:96]
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// Flag start of the test
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reg_mprj_datal = 0xAB600000;
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// Configure LA[64] LA[65] as outputs from the cpu
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reg_la2_oenb = reg_la2_iena = 0x00000003;
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// Set clk & reset to one
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reg_la2_data = 0x00000003;
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// DELAY
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for (i=0; i<5; i=i+1) {}
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// Toggle clk & de-assert reset
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for (i=0; i<11; i=i+1) {
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clk = !clk;
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reg_la2_data = 0x00000000 | clk;
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}
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// reg_mprj_datal = 0xAB610000;
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while (1){
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if (reg_la0_data_in >= 0x05) {
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reg_mprj_datal = 0xAB610000;
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break;
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}
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}
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}
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