From a83f05cf8268182445239844cdcf441aeeb2613a Mon Sep 17 00:00:00 2001 From: cah Date: Wed, 25 Feb 2026 21:08:49 -0700 Subject: [PATCH] fix: sync Yosys-compatible packed LLR interface from chip_ignite Co-Authored-By: Claude Opus 4.6 --- rtl/ldpc_decoder_core.sv | 9 +++++---- rtl/ldpc_decoder_top.sv | 9 ++++----- rtl/wishbone_interface.sv | 4 ++-- 3 files changed, 11 insertions(+), 11 deletions(-) diff --git a/rtl/ldpc_decoder_core.sv b/rtl/ldpc_decoder_core.sv index c3134d0..84451e2 100644 --- a/rtl/ldpc_decoder_core.sv +++ b/rtl/ldpc_decoder_core.sv @@ -30,8 +30,8 @@ module ldpc_decoder_core #( input logic early_term_en, input logic [4:0] max_iter, - // Channel LLRs (loaded before start) - input logic signed [Q-1:0] llr_in [N], + // Channel LLRs (loaded before start) - packed vector for Yosys compatibility + input logic [N*Q-1:0] llr_in, // Status output logic busy, @@ -208,14 +208,15 @@ module ldpc_decoder_core #( INIT: begin // Initialize beliefs from channel LLRs + // Use blocking assignment for array in loop (Verilator requirement) for (int j = 0; j < N; j++) begin - beliefs[j] <= llr_in[j]; + beliefs[j] = $signed(llr_in[j*Q +: Q]); end // Zero all CN->VN messages for (int r = 0; r < M_BASE; r++) for (int c = 0; c < N_BASE; c++) for (int z = 0; z < Z; z++) - msg_cn2vn[r][c][z] <= {Q{1'b0}}; + msg_cn2vn[r][c][z] = {Q{1'b0}}; row_idx <= '0; col_idx <= '0; iter_cnt <= '0; diff --git a/rtl/ldpc_decoder_top.sv b/rtl/ldpc_decoder_top.sv index 638ae4a..3a01a5b 100644 --- a/rtl/ldpc_decoder_top.sv +++ b/rtl/ldpc_decoder_top.sv @@ -15,7 +15,6 @@ module ldpc_decoder_top #( parameter Z = 32, // lifting factor parameter N = N_BASE * Z, // codeword length = 256 parameter K = Z, // info bits = 32 (rate 1/8) - parameter M = M_BASE * Z, // parity checks = 224 parameter Q = 6, // LLR quantization bits (signed) parameter MAX_ITER = 30, // maximum decoding iterations parameter DC = 8, // check node degree (= N_BASE for regular) @@ -50,8 +49,8 @@ module ldpc_decoder_top #( logic stat_converged; logic [4:0] stat_iter_used; - // LLR input buffer (written by host before starting decode) - logic signed [Q-1:0] llr_input [N]; + // LLR input buffer (packed vector for Yosys compatibility) + logic [N*Q-1:0] llr_input_flat; // Decoded output logic [K-1:0] decoded_bits; @@ -75,7 +74,7 @@ module ldpc_decoder_top #( .stat_busy (stat_busy), .stat_converged (stat_converged), .stat_iter_used (stat_iter_used), - .llr_input (llr_input), + .llr_input (llr_input_flat), .decoded_bits (decoded_bits), .syndrome_weight(syndrome_weight), .irq_o (irq_o) @@ -99,7 +98,7 @@ module ldpc_decoder_top #( .start (ctrl_start), .early_term_en (ctrl_early_term), .max_iter (ctrl_max_iter), - .llr_in (llr_input), + .llr_in (llr_input_flat), .busy (stat_busy), .converged (stat_converged), .iter_used (stat_iter_used), diff --git a/rtl/wishbone_interface.sv b/rtl/wishbone_interface.sv index a5ea6f2..2ac8d59 100644 --- a/rtl/wishbone_interface.sv +++ b/rtl/wishbone_interface.sv @@ -32,7 +32,7 @@ module wishbone_interface #( input logic stat_busy, input logic stat_converged, input logic [4:0] stat_iter_used, - output logic signed [Q-1:0] llr_input [N], + output logic [N*Q-1:0] llr_input, // packed LLR vector input logic [K-1:0] decoded_bits, input logic [7:0] syndrome_weight, @@ -99,7 +99,7 @@ module wishbone_interface #( int llr_idx; llr_idx = word_idx * 5 + p; if (llr_idx < N) - llr_input[llr_idx] <= wb_dat_i[p*Q +: Q]; + llr_input[llr_idx*Q +: Q] <= wb_dat_i[p*Q +: Q]; end end end