diff --git a/.gitignore b/.gitignore index 327ee4b..150e770 100644 --- a/.gitignore +++ b/.gitignore @@ -4,3 +4,6 @@ # Python __pycache__/ *.pyc + +# Contest submission repo (separate GitHub repo) +chip_ignite/ diff --git a/docs/plans/2026-02-25-chipfoundry-contest-design.md b/docs/plans/2026-02-25-chipfoundry-contest-design.md new file mode 100644 index 0000000..1fd44ef --- /dev/null +++ b/docs/plans/2026-02-25-chipfoundry-contest-design.md @@ -0,0 +1,274 @@ +# ChipFoundry Reference Application Design Contest — Submission Design + +**Date:** 2026-02-25 +**Contest:** https://chipfoundry.io/challenges/application/ +**Proposal deadline:** March 25, 2026 +**Final submission deadline:** April 30, 2026 +**Tape-out shuttle:** May 13, 2026 + +## Decisions + +| Decision | Choice | +|---|---| +| Application | Free-space optical communication demo | +| Clock target | 50–75 MHz (Sky130) | +| Detector | BAE Systems GMAPD (reference design), cheaper stand-in for demo | +| Demo strategy | Wishbone loopback — PicoRV32 firmware injects LLRs, no optical link | +| Companion processor | PicoRV32 (internal to Caravel) — zero external logic | +| License | Apache 2.0 | +| Approach | A (Minimal Viable Submission), with B and C documented as aspirational | + +--- + +## Approach A: Minimal Viable Submission (EXECUTING) + +Focus on what the judges score: working silicon, verification rigor, and reproducibility. + +### System Architecture + +``` +PicoRV32 (Caravel management SoC) + | + | Internal Wishbone B4 bus + | +ldpc_decoder_top (user project area, ~1.5 mm²) + ├── wishbone_interface — register map, LLR input, decoded output + ├── ldpc_decoder_core — layered offset min-sum, 7x8 QC-LDPC, Z=32 + └── (hard_decision_out) — packed in core already +``` + +**Data flow:** +1. PicoRV32 firmware computes channel LLRs (Poisson model) or loads test vectors +2. Firmware writes 256 quantized 6-bit LLRs to decoder via Wishbone (52 writes, 5 LLRs/word) +3. Firmware writes CTRL register to start decode (max_iter=30, early_term=1) +4. Decoder runs layered min-sum iterations, checks syndrome each iteration +5. Firmware polls STATUS or waits for IRQ +6. Firmware reads 32 decoded bits + syndrome weight via Wishbone +7. Firmware reports results over UART + +**Clock:** Single clock domain — `wb_clk_i` from Caravel, target 50–75 MHz. + +**GPIO usage (minimal for loopback demo):** +- UART TX/RX (2 pins) — already routed through Caravel management SoC +- Optional: 1–2 status LEDs, decode-busy, decode-done +- GMAPD connector footprint: reserved pins for future optical frontend + +**No changes to existing RTL module interfaces needed** — the Wishbone interface already matches Caravel's bus signals. Integration is wiring `ldpc_decoder_top` into `user_project_wrapper.v` in place of `user_proj_example`. + +### Verification Strategy + +Three layers of verification, mapped to contest scoring criteria. + +**Layer 1 — cocotb Functional Tests (in chip_ignite/verilog/dv/cocotb/):** + +| Test | What it proves | +|---|---| +| `ldpc_wb_write_read` | Wishbone register access — write LLRs, read status/version | +| `ldpc_decode_clean` | Decode a valid codeword (zero-noise) — converges in 1 iteration, syndrome=0 | +| `ldpc_decode_noisy` | Decode a noisy codeword (known errors) — converges, matches Python reference | +| `ldpc_decode_max_iter` | Uncorrectable codeword — hits max iterations, syndrome≠0, busy clears | +| `ldpc_early_term` | Early termination enable/disable — verify iteration count differs | +| `ldpc_back_to_back` | Two consecutive decodes without reset — no state leakage | + +**Layer 2 — Python Model Cross-Check:** +- Python model generates test vectors (LLR inputs + expected decoded bits) at multiple SNR points +- cocotb tests load these vectors and compare RTL output bit-exact against Python reference +- Covers the Poisson channel model at lambda_s = 0.5, 1.0, 2.0, 5.0 photons/slot + +**Layer 3 — Gate-Level Simulation (GLS):** +- Re-run Layer 1 tests against post-synthesis netlist (`cf verify --sim gl`) +- Proves the design survives synthesis + place-and-route +- Required by contest rules + +**STA (Static Timing Analysis):** +- SDC constraints targeting 50 MHz (20 ns period) with stretch goal of 75 MHz (13.3 ns) +- Run `make caravel-sta` after hardening +- Report WNS/TNS in documentation + +### Firmware + +Bare-metal C running on PicoRV32 inside Caravel. + +**Functions:** +- `ldpc_load_llrs(int8_t llrs[256])` — packs 5 LLRs per word, writes 52 Wishbone transactions +- `ldpc_start_decode(uint8_t max_iter, bool early_term)` — writes CTRL register +- `ldpc_poll_status()` — spins on STATUS register until busy=0 +- `ldpc_read_result(uint32_t *decoded, uint16_t *syndrome_wt, uint8_t *iters)` — reads output registers +- `uart_print_result()` — formats and prints to UART for demo + +**Demo scenarios (run sequentially on boot):** +1. **Clean codeword** — encode known 32-bit message, load as perfect LLRs, decode, verify. Prints: `PASS: clean decode, 1 iteration` +2. **Noisy codeword** — pre-stored test vector with known errors, decode, verify. Prints: `PASS: noisy decode, 8 iterations, syndrome=0` +3. **Stress test** — loop 100 decodes with different pre-stored vectors, report pass/fail count and average iterations + +No LLR computation from optical data in firmware — that's future work (Approach B/C). All test vectors are compiled into the firmware binary. + +Build: Standard Caravel firmware Makefile (GCC cross-compile for RV32I, link against Caravel BSP). + +### PCBA Reference Design + +Two-part board design in KiCad. + +**Part A — Fabricated for demo (minimal breakout):** +- Caravel QFN-64 socket with proper decoupling (1.8V core, 3.3V I/O) +- 25 MHz crystal oscillator (Caravel reference clock) +- 3.3V and 1.8V LDO regulators (USB-powered or barrel jack) +- FTDI USB-UART bridge for firmware console +- SPI flash for firmware storage +- Reset button, power LED, 2x status LEDs +- 2-layer board, standard FR4, JLCPCB-friendly + +**Part B — Documented but unpopulated (optical frontend):** +- GMAPD connector footprint (BAE Systems detector interface) +- TIA (transimpedance amplifier) section — reference schematic with AD8015 or similar +- Comparator/discriminator — converts analog pulse to digital timestamp +- Bias voltage supply for GMAPD (high-voltage section, isolated) +- SMA connector for external clock sync +- All components in BOM with Digi-Key part numbers, but DNP for initial build + +**Board size:** ~50x80mm, fits a standard 3D-printed enclosure. + +**Mechanical:** Simple 3D-printed box (OpenSCAD parametric), standoffs for PCB mount, cutouts for USB, barrel jack, and SMA. STL files included in repo. + +### OpenLane Hardening & Tape-out Flow + +**Macro hardening (`ldpc_decoder_top`):** +- Copy RTL files into `chip_ignite/verilog/rtl/` +- Create `chip_ignite/openlane/ldpc_decoder_top/config.json`: + - `CLOCK_PERIOD`: 20 ns (50 MHz), tighten to 13.3 ns (75 MHz) if timing allows + - `CLOCK_PORT`: `wb_clk_i` + - `DIE_AREA`: sized for ~1.5 mm² (~1200x1250 um) + - Sky130 standard cells, no hard macros (all SRAM is register-based) +- Pin ordering config matching wrapper placement +- SDC constraints with input/output delays for Wishbone interface + +**Wrapper integration (`user_project_wrapper`):** +- Replace `user_proj_example` instantiation with `ldpc_decoder_top` +- Update macro placement coordinates in wrapper `config.json` +- Point to hardened GDS/LEF/netlist/SPEF + +**Flow sequence:** +``` +cf harden ldpc_decoder_top # Synthesize + P&R the decoder +cf harden user_project_wrapper # Integrate into Caravel +cf gpio-config # Configure GPIO modes +cf verify --all # RTL + GL sim +cf precheck # Shuttle compliance +``` + +**Timing closure strategy:** +- Start at 50 MHz (20 ns) — likely first-pass clean +- If WNS > 5 ns, tighten to 75 MHz (13.3 ns) +- If negative WNS at 75 MHz, pipeline the critical path (CN update min-finding) and retry +- Document achieved frequency in final submission + +### Contest Deliverables + +**Proposal (due Mar 25):** +- GitHub repo (`chip_ignite`) with README describing the project +- Project description: LDPC decoder for photon-starved optical comm +- Architecture overview, target specs, verification plan + +**Final Submission (due Apr 30):** + +| Deliverable | Source | +|---|---| +| GDSII | OpenLane output from `cf harden` | +| RTL + testbenches | `chip_ignite/verilog/rtl/` and `verilog/dv/cocotb/` | +| Gate-level sim passing | `cf verify --all --sim gl` | +| Precheck passing | `cf precheck` | +| Firmware source | `chip_ignite/firmware/ldpc_demo/` | +| PCBA design (KiCad) | `chip_ignite/pcba/` | +| Mechanical (OpenSCAD) | `chip_ignite/mechanical/` | +| 3-min demo video | Screen recording of UART decode output + GDS viewer walkthrough | +| Screenshots (how-to) | Step-by-step: build firmware, program, run demo | +| Apache 2.0 LICENSE | Repo root | +| AI disclosure | `docs/ai-disclosure.md` — Claude session logs and prompts | + +### Timeline + +**Week 1 (Feb 25 – Mar 3): Integration & Verification Foundation** +- Integrate RTL into chip_ignite template (wire into `user_project_wrapper.v`) +- Generate test vectors from Python model +- Write cocotb testbenches (all 6 functional tests) +- Verify RTL simulation passes via `cf verify` + +**Week 2 (Mar 3 – Mar 10): OpenLane Hardening** +- Create OpenLane config for `ldpc_decoder_top` +- First synthesis + P&R run at 50 MHz +- Debug DRC/LVS issues +- Run STA, document WNS/TNS + +**Week 3 (Mar 10 – Mar 17): Gate-Level Sim & Timing Push** +- Gate-level simulation of all cocotb tests +- If timing margin exists, push toward 75 MHz +- Pipeline critical paths if needed +- Pass `cf precheck` + +**Week 4 (Mar 17 – Mar 25): PROPOSAL DEADLINE** +- Polish README with architecture, specs, verification status +- Submit proposal (repo URL via contest form) +- Start firmware development in parallel + +**Week 5 (Mar 25 – Apr 7): Firmware & PCBA** +- Write PicoRV32 firmware (LLR load, decode, UART output) +- Design PCBA schematic in KiCad (breakout + optical frontend reference) +- Start PCB layout + +**Week 6 (Apr 7 – Apr 14): PCBA & Mechanical** +- Complete PCB layout, generate Gerbers +- Design 3D-printed enclosure in OpenSCAD +- BOM with Digi-Key part numbers and costs + +**Week 7 (Apr 14 – Apr 21): Documentation & Demo** +- AI disclosure document +- Verification report +- Record 3-min demo video (cocotb sim + GDS walkthrough) +- How-to screenshots + +**Week 8 (Apr 21 – Apr 30): FINAL SUBMISSION** +- Final `cf precheck` pass +- Polish all docs +- Submit + +**Buffer:** ~1 week of slack distributed across weeks 5–7. Critical path is weeks 1–3 (RTL integration → hardening → GLS). + +--- + +## Approach B: Full Reference Design (ASPIRATIONAL) + +Everything in Approach A, plus: + +- **Populated optical frontend** on PCBA — SiPM stand-in (e.g. ON Semi C-Series MicroFC) + TIA (AD8015) + fast comparator (ADCMP607). Analog section designed for single-photon pulse detection. +- **External MCU** (RP2040) on PCBA for real-time LLR computation from detector output. Receives photon count data, computes Poisson channel LLRs, feeds to Caravel ASIC over SPI. +- **Actual free-space optical link demo** — modulated laser diode TX (OOK or PPM), receiver board with populated optical frontend, ~1–5m bench-scale link. +- **More elaborate enclosure** with lens mount (aspheric collimating lens), detector alignment rail, and laser safety labeling. +- **Firmware targets:** Both PicoRV32 (ASIC-internal decode control) and RP2040 (external LLR computation + system orchestration). + +**Additional BOM cost:** ~$50–100 per unit (SiPM module, TIA, laser diode, lens, RP2040 board). + +**Additional effort:** ~4–6 weeks beyond Approach A. Requires analog PCB design expertise and optical alignment work. + +--- + +## Approach C: Silicon-First, Board-Later (ASPIRATIONAL) + +Chip is identical to Approach A (fully hardened, precheck-clean). Difference is in the board and demo: + +- **PCBA:** Full schematic and layout complete in KiCad (includes optical frontend from Approach B), but untested — silicon doesn't return until Oct/Nov 2026. +- **Firmware:** Compiles and links against Caravel BSP, but validated only in simulation (cocotb + Verilator), not on hardware. +- **Demo video:** cocotb simulation showing full decode pipeline + OpenLane GDS walkthrough + KiCad 3D board render. No hardware demo. +- **Mechanical:** Full enclosure design with detector mount, but 3D-printed prototype deferred until silicon arrives. + +**Rationale:** Acknowledges that no contestant can demo on real silicon by April 30 — the shuttle doesn't return until Oct/Nov. Puts all effort into a clean tape-out and thorough documentation, with the physical build planned for silicon return. + +--- + +## Long-Term Vision + +After silicon returns (Oct/Nov 2026): +1. Build and populate full Approach B board +2. Demonstrate free-space optical link with BAE GMAPD detector +3. Characterize decoder BER performance on real silicon vs. simulation +4. Publish results as open-source reference design for photon-starved optical comm +5. Target applications: CubeSat optical downlinks, underwater optical modems, quantum key distribution post-processing