.cf/project.json was stale at 13h1809 (mgmt_output) — sync with
user_defines.v and gpio_defaults_block_1800.v which already specify
USER_STD_BIDIRECTIONAL. Verified via cf gpio-config --view:
user_bidirectional 33 5-37
Caravel mgmt GPIOs 0-4 unchanged.
Co-Authored-By: Claude Opus 4.7 (1M context) <noreply@anthropic.com>
- CubeSat power: "1-5 W total" -> "7-20 W total, 2-5 W comms payload"
- 650 nm laser: add IEC 60825-1 Class 1 designation and power limit
- JLCPCB pricing: clarify "$2 for 5 boards" not "$2/board"
- DAPD PNR at 1550 nm: add caveat about InGaAs resolution limits
(~tens of photons vs single-photon at visible wavelengths)
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
Add advanced detector configuration showing integration path for
BAE Systems GMAPD and ATI DAPD single-photon detectors. Explains
why photon-number-resolving detectors exploit the decoder's
soft-input architecture more fully than binary click/no-click
detection. No ASIC changes required — same 6-bit LLR interface.
Opens 1550 nm telecom-compatible deployment scenarios.
Co-Authored-By: Claude Opus 4.6 (1M context) <noreply@anthropic.com>
BLKSEQ: intentional blocking assigns in sequential logic for Yosys
BLKLOOPINIT compatibility. UNUSEDPARAM/CASEINCOMPLETE: known benign.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
BLKSEQ: intentional blocking assigns in sequential logic for Yosys
BLKLOOPINIT compatibility. UNUSEDPARAM/CASEINCOMPLETE: known benign.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
The template CI tried to re-harden from scratch in GitHub Actions, but
cf harden requires a TTY for Docker and the design takes 8+ hours.
Replace with a Verilator lint check. Hardening and precheck are run
locally on snoke; GDS/SPEF are uploaded via cf push.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Demo firmware runs clean decode + noisy decode (vector 0) and reports
pass/fail on GPIO[7:0]. All 5 cocotb tests pass: ldpc_basic, ldpc_noisy,
ldpc_max_iter, ldpc_back_to_back, and ldpc_demo.
Also adds .cf/project.json with GPIO configuration.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Use overflow detection instead of $signed comparison.
Use function assignment instead of return statements.
Yosys parser can't handle return with complex concatenation.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Yosys doesn't support unpacked array ports. Changed llr_in/llr_input
from `logic signed [Q-1:0] llr[N]` to `logic [N*Q-1:0] llr` packed
vector. Also fixed blocking assignment in INIT loops (Verilator
BLKLOOPINIT requirement).
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Replace unpacked array parameter with 8 individual ports.
Icarus Verilog (used by cocotb) doesn't support unpacked
dimensions in task/function ports.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- config.json: 20ns clock period, AREA 2 synth strategy, 2800x1760um die
- pin_order.cfg: Wishbone pins on south, outputs on north
- base_ldpc.sdc: Caravel-calibrated timing constraints adapted for LDPC ports
- Updated wrapper config to reference ldpc_decoder_top macro
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Magnitude overflow for -32 in cn_min_sum (clamp to 31)
- Converged flag cleared prematurely in IDLE (move to INIT)
- msg_cn2vn zeroing race in first iteration (bypass old_msg read)
All 20 test vectors now pass bit-exact against Python model.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Prevents magnitude 0 from unconnected columns dominating the
minimum computation and zeroing all CN->VN messages.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add test_data.py (cocotb Python module) and test_vectors.h (C header)
with 20 test vectors from the Python behavioral model. LLR data is
packed 5 per 32-bit word matching the wishbone interface format.
11 converged vectors for positive testing, 9 non-converged for
negative testing.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
- Copy ldpc_decoder_core.sv and wishbone_interface.sv from standalone RTL
- Create Caravel-adapted ldpc_decoder_top.sv with USE_POWER_PINS,
32-bit address (lower 8 bits passed through), and wb_sel_i port
- Replace user_proj_example in user_project_wrapper.v with LDPC decoder
instantiation, active-high to active-low reset inversion, and tie-offs
for unused outputs (la_data_out, io_out, io_oeb, user_irq[2:1])
- Update includes.rtl.caravel_user_project with LDPC RTL file list
- Fix invalid hex literal in VERSION_ID (0xLD -> 0x1D)
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
