29 lines
1.6 KiB
Markdown
29 lines
1.6 KiB
Markdown
# AI Disclosure
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This project was developed with assistance from Claude (Anthropic), an AI coding assistant.
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## How AI Was Used
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- **RTL design and debugging**: AI assisted with SystemVerilog implementation of the LDPC decoder core, Wishbone interface, and Caravel integration wrapper. AI-driven verification found and fixed 7 RTL bugs through standalone and vector-driven testbenches.
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- **Behavioral modeling**: Python simulation model (density evolution, BER analysis, test vector generation) co-developed with AI assistance.
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- **Build system and tooling**: OpenLane configuration, SDC timing constraints, and Makefile setup guided by AI.
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- **Documentation**: Architecture docs, project reports, and contest submission materials drafted with AI assistance.
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- **Design space exploration**: Code rate comparison, base matrix optimization, SC-LDPC analysis performed with AI-guided Python scripts.
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## Human Contributions
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All architectural decisions, algorithm selection (layered offset min-sum, QC-LDPC rate 1/8, IRA staircase structure), target application (photon-starved optical communication), and final design review were made by the human designer. The AI served as a coding assistant, technical reference, and verification tool.
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## Transparency
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Full conversation transcripts with the AI assistant are available upon request. Key AI-assisted files include:
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- `verilog/rtl/*.sv` — RTL implementation
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- `../model/*.py` — Python behavioral model (in parent ldpc_optical repo)
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- `openlane/*/config.json` — Synthesis configuration
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- `docs/` — Documentation
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## Tool
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- **AI Model**: Claude (Anthropic) via Claude Code CLI
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- **Usage Period**: February 2026
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