146 lines
7.1 KiB
Tcl
146 lines
7.1 KiB
Tcl
# generated by get_cup_sdc.py
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# Date: 2023/06/20
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### Note:
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# - input clock transition and latency are set for wb_clk_i port.
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# If your design is using the user_clock2, update the clock constraints to reflect that and use usr_* variables.
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# - IO ports are assumed to be asynchronous. If they're synchronous to the clock, update the variable IO_SYNC to 1.
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# As well, update in_ext_delay and out_ext_delay with the required I/O external delays.
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#------------------------------------------#
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# Pre-defined Constraints
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#------------------------------------------#
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set ::env(IO_SYNC) 0
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# Clock network
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if {[info exists ::env(CLOCK_PORT)] && $::env(CLOCK_PORT) != ""} {
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set clk_input $::env(CLOCK_PORT)
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create_clock [get_ports $clk_input] -name clk -period $::env(CLOCK_PERIOD)
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puts "\[INFO\]: Creating clock {clk} for port $clk_input with period: $::env(CLOCK_PERIOD)"
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} else {
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set clk_input __VIRTUAL_CLK__
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create_clock -name clk -period $::env(CLOCK_PERIOD)
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puts "\[INFO\]: Creating virtual clock with period: $::env(CLOCK_PERIOD)"
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}
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if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL)] } {
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set ::env(SYNTH_CLK_DRIVING_CELL) $::env(SYNTH_DRIVING_CELL)
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}
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if { ![info exists ::env(SYNTH_CLK_DRIVING_CELL_PIN)] } {
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set ::env(SYNTH_CLK_DRIVING_CELL_PIN) $::env(SYNTH_DRIVING_CELL_PIN)
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}
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# Clock non-idealities
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set_propagated_clock [all_clocks]
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set_clock_uncertainty $::env(SYNTH_CLOCK_UNCERTAINTY) [get_clocks {clk}]
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puts "\[INFO\]: Setting clock uncertainity to: $::env(SYNTH_CLOCK_UNCERTAINTY)"
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set_clock_transition $::env(SYNTH_CLOCK_TRANSITION) [get_clocks {clk}]
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puts "\[INFO\]: Setting clock transition to: $::env(SYNTH_CLOCK_TRANSITION)"
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# Maximum transition time for the design nets
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set_max_transition $::env(MAX_TRANSITION_CONSTRAINT) [current_design]
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puts "\[INFO\]: Setting maximum transition to: $::env(MAX_TRANSITION_CONSTRAINT)"
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# Maximum fanout
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set_max_fanout $::env(MAX_FANOUT_CONSTRAINT) [current_design]
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puts "\[INFO\]: Setting maximum fanout to: $::env(MAX_FANOUT_CONSTRAINT)"
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# Timing paths delays derate
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set_timing_derate -early [expr {1-$::env(SYNTH_TIMING_DERATE)}]
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set_timing_derate -late [expr {1+$::env(SYNTH_TIMING_DERATE)}]
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puts "\[INFO\]: Setting timing derate to: [expr {$::env(SYNTH_TIMING_DERATE) * 100}] %"
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# Reset input delay
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set_input_delay [expr $::env(CLOCK_PERIOD) * 0.5] -clock [get_clocks {clk}] [get_ports {wb_rst_i}]
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# Multicycle paths
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set_multicycle_path -setup 2 -through [get_ports {wbs_ack_o}]
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set_multicycle_path -hold 1 -through [get_ports {wbs_ack_o}]
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set_multicycle_path -setup 2 -through [get_ports {wbs_cyc_i}]
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set_multicycle_path -hold 1 -through [get_ports {wbs_cyc_i}]
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set_multicycle_path -setup 2 -through [get_ports {wbs_stb_i}]
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set_multicycle_path -hold 1 -through [get_ports {wbs_stb_i}]
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#------------------------------------------#
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# Retrieved Constraints
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#------------------------------------------#
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# Clock source latency
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set usr_clk_max_latency 4.57
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set usr_clk_min_latency 4.11
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set clk_max_latency 5.57
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set clk_min_latency 4.65
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set_clock_latency -source -max $clk_max_latency [get_clocks {clk}]
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set_clock_latency -source -min $clk_min_latency [get_clocks {clk}]
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puts "\[INFO\]: Setting clock latency range: $clk_min_latency : $clk_max_latency"
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# Clock input Transition
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set usr_clk_tran 0.13
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set clk_tran 0.61
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set_input_transition $clk_tran [get_ports $clk_input]
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puts "\[INFO\]: Setting clock transition: $clk_tran"
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# Input delays
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set_input_delay -max 1.87 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
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set_input_delay -max 1.89 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
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set_input_delay -max 3.17 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
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set_input_delay -max 3.74 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
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set_input_delay -max 3.89 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
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set_input_delay -max 4.13 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
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set_input_delay -max 4.61 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
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set_input_delay -max 4.74 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
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set_input_delay -min 0.18 -clock [get_clocks {clk}] [get_ports {la_data_in[*]}]
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set_input_delay -min 0.3 -clock [get_clocks {clk}] [get_ports {la_oenb[*]}]
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set_input_delay -min 0.79 -clock [get_clocks {clk}] [get_ports {wbs_adr_i[*]}]
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set_input_delay -min 1.04 -clock [get_clocks {clk}] [get_ports {wbs_dat_i[*]}]
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set_input_delay -min 1.19 -clock [get_clocks {clk}] [get_ports {wbs_sel_i[*]}]
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set_input_delay -min 1.65 -clock [get_clocks {clk}] [get_ports {wbs_we_i}]
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set_input_delay -min 1.69 -clock [get_clocks {clk}] [get_ports {wbs_cyc_i}]
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set_input_delay -min 1.86 -clock [get_clocks {clk}] [get_ports {wbs_stb_i}]
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if { $::env(IO_SYNC) } {
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set in_ext_delay 4
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puts "\[INFO\]: Setting input ports external delay to: $in_ext_delay"
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set_input_delay -max [expr $in_ext_delay + 4.55] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
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set_input_delay -min [expr $in_ext_delay + 1.26] -clock [get_clocks {clk}] [get_ports {io_in[*]}]
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}
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# Input Transition
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set_input_transition -max 0.14 [get_ports {wbs_we_i}]
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set_input_transition -max 0.15 [get_ports {wbs_stb_i}]
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set_input_transition -max 0.17 [get_ports {wbs_cyc_i}]
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set_input_transition -max 0.18 [get_ports {wbs_sel_i[*]}]
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set_input_transition -max 0.38 [get_ports {io_in[*]}]
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set_input_transition -max 0.84 [get_ports {wbs_dat_i[*]}]
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set_input_transition -max 0.86 [get_ports {la_data_in[*]}]
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set_input_transition -max 0.92 [get_ports {wbs_adr_i[*]}]
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set_input_transition -max 0.97 [get_ports {la_oenb[*]}]
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set_input_transition -min 0.05 [get_ports {io_in[*]}]
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set_input_transition -min 0.06 [get_ports {la_oenb[*]}]
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set_input_transition -min 0.07 [get_ports {la_data_in[*]}]
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set_input_transition -min 0.07 [get_ports {wbs_adr_i[*]}]
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set_input_transition -min 0.07 [get_ports {wbs_dat_i[*]}]
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set_input_transition -min 0.09 [get_ports {wbs_cyc_i}]
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set_input_transition -min 0.09 [get_ports {wbs_sel_i[*]}]
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set_input_transition -min 0.09 [get_ports {wbs_we_i}]
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set_input_transition -min 0.15 [get_ports {wbs_stb_i}]
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# Output delays
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set_output_delay -max 0.7 -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
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set_output_delay -max 1.0 -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
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set_output_delay -max 3.62 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
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set_output_delay -max 8.41 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
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set_output_delay -min 0 -clock [get_clocks {clk}] [get_ports {la_data_out[*]}]
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set_output_delay -min 0 -clock [get_clocks {clk}] [get_ports {user_irq[*]}]
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set_output_delay -min 1.13 -clock [get_clocks {clk}] [get_ports {wbs_dat_o[*]}]
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set_output_delay -min 1.37 -clock [get_clocks {clk}] [get_ports {wbs_ack_o}]
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if { $::env(IO_SYNC) } {
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set out_ext_delay 4
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puts "\[INFO\]: Setting output ports external delay to: $out_ext_delay"
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set_output_delay -max [expr $out_ext_delay + 9.12] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
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set_output_delay -max [expr $out_ext_delay + 9.32] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
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set_output_delay -min [expr $out_ext_delay + 2.34] -clock [get_clocks {clk}] [get_ports {io_oeb[*]}]
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set_output_delay -min [expr $out_ext_delay + 3.9] -clock [get_clocks {clk}] [get_ports {io_out[*]}]
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}
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# Output loads
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set_load 0.19 [all_outputs]
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