cah 81cffda1cb feat: add OpenLane hardening config for LDPC decoder (50 MHz) ...

- config.json: 20ns clock period, AREA 2 synth strategy, 2800x1760um die
- pin_order.cfg: Wishbone pins on south, outputs on north
- base_ldpc.sdc: Caravel-calibrated timing constraints adapted for LDPC ports
- Updated wrapper config to reference ldpc_decoder_top macro

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-02-25 20:08:39 -07:00

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