cah
81cffda1cb
- config.json: 20ns clock period, AREA 2 synth strategy, 2800x1760um die - pin_order.cfg: Wishbone pins on south, outputs on north - base_ldpc.sdc: Caravel-calibrated timing constraints adapted for LDPC ports - Updated wrapper config to reference ldpc_decoder_top macro Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
70 lines
1.8 KiB
JSON
70 lines
1.8 KiB
JSON
{
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"DESIGN_NAME": "ldpc_decoder_top",
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"FP_PDN_MULTILAYER": false,
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"VERILOG_FILES": [
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"dir::../../verilog/rtl/defines.v",
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"dir::../../verilog/rtl/ldpc_decoder_top.sv",
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"dir::../../verilog/rtl/ldpc_decoder_core.sv",
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"dir::../../verilog/rtl/wishbone_interface.sv"
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],
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"CLOCK_PERIOD": 20,
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"CLOCK_PORT": "clk",
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"CLOCK_NET": "u_core.clk",
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"FP_SIZING": "absolute",
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"DIE_AREA": [
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0,
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0,
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2800,
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1760
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],
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"FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
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"MAX_TRANSITION_CONSTRAINT": 1.5,
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"MAX_FANOUT_CONSTRAINT": 16,
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"PL_RESIZER_SETUP_SLACK_MARGIN": 0.4,
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"GRT_RESIZER_SETUP_SLACK_MARGIN": 0.2,
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"GRT_RESIZER_HOLD_SLACK_MARGIN": 0.2,
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"PL_RESIZER_HOLD_SLACK_MARGIN": 0.4,
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"CTS_CLK_MAX_WIRE_LENGTH": 500,
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"MAGIC_DEF_LABELS": false,
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"SYNTH_ABC_BUFFERING": false,
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"RUN_HEURISTIC_DIODE_INSERTION": true,
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"HEURISTIC_ANTENNA_THRESHOLD": 110,
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"RUN_ANTENNA_REPAIR": true,
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"RUN_POST_GRT_DESIGN_REPAIR": true,
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"RUN_POST_GRT_RESIZER_TIMING": true,
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"VDD_NETS": [
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"vccd1"
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],
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"GND_NETS": [
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"vssd1"
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],
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"FALLBACK_SDC_FILE": "dir::base_ldpc.sdc",
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"MAGIC_DRC_USE_GDS": true,
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"DPL_CELL_PADDING": 2,
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"GPL_CELL_PADDING": 2,
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"SYNTH_STRATEGY": "AREA 2",
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"PL_TARGET_DENSITY_PCT": 40,
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"pdk::sky130*": {
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"RT_MAX_LAYER": "met4",
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"scl::sky130_fd_sc_hd": {
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"CLOCK_PERIOD": 20
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},
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"scl::sky130_fd_sc_hdll": {
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"CLOCK_PERIOD": 10
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},
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"scl::sky130_fd_sc_hs": {
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"CLOCK_PERIOD": 8
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},
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"scl::sky130_fd_sc_ls": {
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"CLOCK_PERIOD": 10,
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"SYNTH_MAX_FANOUT": 5
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},
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"scl::sky130_fd_sc_ms": {
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"CLOCK_PERIOD": 10
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}
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},
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"meta": {
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"version": 2
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}
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}
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