cah
fdd68bb76b
RTL: Split CN_UPDATE into pipelined CN_STAGE1/CN_STAGE2, replace serial popcount with balanced adder tree for timing closure. Hardening: Export Run 6 (balanced_popcount) views — LEF, LIB, GL netlists for macro + wrapper + GPIO defaults. GDS/DEF/SPEF kept local (cf push). TT WNS = +3.28ns at 50 MHz. DRC/LVS clean. Config: Increase SDC min input delays +0.7ns (fix 1,543 hold violations). Set ERROR_ON_LVS_ERROR=false for wrapper cosmetic pin-match. Fix GPIO defines to GPIO_MODE_USER_STD_BIDIRECTIONAL. Verification: 5/5 GLS tests pass, 17/19 precheck pass. Add SPDX headers, GLS test runner, OpenLane helper scripts. Update README with results. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
113 lines
3.3 KiB
JSON
113 lines
3.3 KiB
JSON
{
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"//": "Design files",
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"VERILOG_FILES": [
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"dir::../../verilog/rtl/defines.v",
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"dir::../../verilog/rtl/user_project_wrapper.v"
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],
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"PNR_SDC_FILE": "dir::signoff.sdc",
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"//": "Hardening strategy variables (this is for 1-Macro-First Hardening). Visit https://docs.google.com/document/d/1pf-wbpgjeNEM-1TcvX2OJTkHjqH_C9p-LURCASS0Zo8 for more info",
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"SYNTH_ELABORATE_ONLY": true,
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"RUN_POST_GPL_DESIGN_REPAIR": false,
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"RUN_POST_CTS_RESIZER_TIMING": false,
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"DESIGN_REPAIR_BUFFER_INPUT_PORTS": false,
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"FP_PDN_ENABLE_RAILS": true,
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"RUN_ANTENNA_REPAIR": false,
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"RUN_FILL_INSERTION": true,
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"RUN_TAP_ENDCAP_INSERTION": true,
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"RUN_CTS": false,
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"RUN_IRDROP_REPORT": false,
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"ERROR_ON_SYNTH_CHECKS": false,
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"ERROR_ON_UNMAPPED_CELLS": false,
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"ERROR_ON_NL_ASSIGN_STATEMENTS": false,
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"ERROR_ON_MAGIC_DRC": true,
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"ERROR_ON_LVS_ERROR": false,
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"HOLD_VIOLATION_CORNERS": [""],
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"//": "Macros configurations",
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"MACROS": {
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"ldpc_decoder_top": {
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"gds": [
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"dir::../../gds/ldpc_decoder_top.gds"
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],
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"lef": [
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"dir::../../lef/ldpc_decoder_top.lef"
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],
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"instances": {
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"mprj": {
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"location": [60, 15],
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"orientation": "N"
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}
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},
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"nl": [
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"dir::../../verilog/gl/ldpc_decoder_top.v"
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],
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"spef": {
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"min_*": [
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"dir::../../spef/multicorner/ldpc_decoder_top.min.spef"
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],
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"nom_*": [
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"dir::../../spef/multicorner/ldpc_decoder_top.nom.spef"
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],
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"max_*": [
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"dir::../../spef/multicorner/ldpc_decoder_top.max.spef"
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]
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},
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"lib": {
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"*": "dir::../../lib/ldpc_decoder_top.lib"
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}
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}
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},
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"PDN_MACRO_CONNECTIONS": ["mprj vccd2 vssd2 vccd1 vssd1"],
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"//": "PDN configurations",
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"FP_PDN_VOFFSET": 5,
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"FP_PDN_HOFFSET": 5,
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"FP_PDN_VWIDTH": 3.1,
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"FP_PDN_HWIDTH": 3.1,
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"FP_PDN_VSPACING": 15.5,
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"FP_PDN_HSPACING": 15.5,
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"FP_PDN_VPITCH": 180,
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"FP_PDN_HPITCH": 180,
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"ERROR_ON_PDN_VIOLATIONS": false,
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"//": "Magic variables",
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"MAGIC_DRC_USE_GDS": true,
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"DRT_THREADS": 1,
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"MAX_TRANSITION_CONSTRAINT": 1.5,
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"//": "Fixed configurations for caravel. You should NOT edit this section",
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"DESIGN_NAME": "user_project_wrapper",
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"FP_SIZING": "absolute",
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"DIE_AREA": [0, 0, 2920, 3520],
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"FP_DEF_TEMPLATE": "dir::fixed_dont_change/user_project_wrapper.def",
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"VDD_NETS": [
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"vccd1",
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"vccd2",
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"vdda1",
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"vdda2"
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],
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"GND_NETS": [
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"vssd1",
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"vssd2",
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"vssa1",
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"vssa2"
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],
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"FP_PDN_CORE_RING": true,
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"FP_PDN_CORE_RING_VWIDTH": 3.1,
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"FP_PDN_CORE_RING_HWIDTH": 3.1,
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"FP_PDN_CORE_RING_VOFFSET": 12.45,
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"FP_PDN_CORE_RING_HOFFSET": 12.45,
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"FP_PDN_CORE_RING_VSPACING": 1.7,
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"FP_PDN_CORE_RING_HSPACING": 1.7,
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"CLOCK_PORT": "wb_clk_i",
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"SIGNOFF_SDC_FILE": "dir::signoff.sdc",
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"MAGIC_DEF_LABELS": false,
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"CLOCK_PERIOD": 25,
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"MAGIC_ZEROIZE_ORIGIN": false,
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"meta": {
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"version": 2
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}
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}
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