cah
fdd68bb76b
RTL: Split CN_UPDATE into pipelined CN_STAGE1/CN_STAGE2, replace serial popcount with balanced adder tree for timing closure. Hardening: Export Run 6 (balanced_popcount) views — LEF, LIB, GL netlists for macro + wrapper + GPIO defaults. GDS/DEF/SPEF kept local (cf push). TT WNS = +3.28ns at 50 MHz. DRC/LVS clean. Config: Increase SDC min input delays +0.7ns (fix 1,543 hold violations). Set ERROR_ON_LVS_ERROR=false for wrapper cosmetic pin-match. Fix GPIO defines to GPIO_MODE_USER_STD_BIDIRECTIONAL. Verification: 5/5 GLS tests pass, 17/19 precheck pass. Add SPDX headers, GLS test runner, OpenLane helper scripts. Update README with results. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
31 lines
612 B
JSON
31 lines
612 B
JSON
{
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"TOP_SOURCE": "user_project_wrapper",
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"TOP_LAYOUT": "$TOP_SOURCE",
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"EXTRACT_FLATGLOB": [
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""
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],
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"EXTRACT_ABSTRACT": [
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"*__fill_*",
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"*__fakediode_*",
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"*__tapvpwrvgnd_*"
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],
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"LVS_FLATTEN": [
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""
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],
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"LVS_NOFLATTEN": [
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""
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],
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"LVS_IGNORE": [
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""
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],
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"LVS_SPICE_FILES": [
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"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap*.spice",
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"$PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice"
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],
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"LVS_VERILOG_FILES": [
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"$UPRJ_ROOT/verilog/gl/ldpc_decoder_top.v",
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"$UPRJ_ROOT/verilog/gl/$TOP_SOURCE.v"
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],
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"LAYOUT_FILE": "$UPRJ_ROOT/gds/$TOP_LAYOUT.gds"
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}
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