chip_ignite/signoff/user_proj_example/metrics.csv

1	Metric	Value
2	design__lint_error__count	0
3	design__lint_timing_construct__count	0
4	design__lint_warning__count	8
5	design__inferred_latch__count	0
6	design__instance__count	70590
7	design__instance__area	95369
8	design__instance_unmapped__count	0
9	synthesis__check_error__count	0
10	design__max_slew_violation__count__corner:nom_tt_025C_1v80	4
11	design__max_fanout_violation__count__corner:nom_tt_025C_1v80	14
12	design__max_cap_violation__count__corner:nom_tt_025C_1v80	0
13	power__internal__total	0.00019559991778805852
14	power__switching__total	0.000429551990237087
15	power__leakage__total	1.919598524580124E-8
16	power__total	0.000625171116553247
17	clock__skew__worst_hold__corner:nom_tt_025C_1v80	-2.096730848291461
18	clock__skew__worst_setup__corner:nom_tt_025C_1v80	3.154773864771945
19	timing__hold__ws__corner:nom_tt_025C_1v80	0.3478915032298054
20	timing__setup__ws__corner:nom_tt_025C_1v80	7.060046969096608
21	timing__hold__tns__corner:nom_tt_025C_1v80	0.0
22	timing__setup__tns__corner:nom_tt_025C_1v80	0.0
23	timing__hold__wns__corner:nom_tt_025C_1v80	0
24	timing__setup__wns__corner:nom_tt_025C_1v80	0.0
25	timing__hold_vio__count__corner:nom_tt_025C_1v80	0
26	timing__hold_r2r__ws__corner:nom_tt_025C_1v80	1.019479
27	timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80	0
28	timing__setup_vio__count__corner:nom_tt_025C_1v80	0
29	timing__setup_r2r__ws__corner:nom_tt_025C_1v80	Infinity
30	timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80	0
31	design__max_slew_violation__count__corner:nom_ss_100C_1v60	174
32	design__max_fanout_violation__count__corner:nom_ss_100C_1v60	14
33	design__max_cap_violation__count__corner:nom_ss_100C_1v60	1
34	clock__skew__worst_hold__corner:nom_ss_100C_1v60	-2.0973783303777345
35	clock__skew__worst_setup__corner:nom_ss_100C_1v60	3.0085152998174016
36	timing__hold__ws__corner:nom_ss_100C_1v60	1.0258354456252161
37	timing__setup__ws__corner:nom_ss_100C_1v60	2.4240024007463363
38	timing__hold__tns__corner:nom_ss_100C_1v60	0.0
39	timing__setup__tns__corner:nom_ss_100C_1v60	0.0
40	timing__hold__wns__corner:nom_ss_100C_1v60	0
41	timing__setup__wns__corner:nom_ss_100C_1v60	0.0
42	timing__hold_vio__count__corner:nom_ss_100C_1v60	0
43	timing__hold_r2r__ws__corner:nom_ss_100C_1v60	2.235596
44	timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60	0
45	timing__setup_vio__count__corner:nom_ss_100C_1v60	0
46	timing__setup_r2r__ws__corner:nom_ss_100C_1v60	Infinity
47	timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60	0
48	design__max_slew_violation__count__corner:nom_ff_n40C_1v95	0
49	design__max_fanout_violation__count__corner:nom_ff_n40C_1v95	14
50	design__max_cap_violation__count__corner:nom_ff_n40C_1v95	0
51	clock__skew__worst_hold__corner:nom_ff_n40C_1v95	-2.0964635065795703
52	clock__skew__worst_setup__corner:nom_ff_n40C_1v95	3.25268488017196
53	timing__hold__ws__corner:nom_ff_n40C_1v95	0.25673464081342046
54	timing__setup__ws__corner:nom_ff_n40C_1v95	8.431948711247525
55	timing__hold__tns__corner:nom_ff_n40C_1v95	0.0
56	timing__setup__tns__corner:nom_ff_n40C_1v95	0.0
57	timing__hold__wns__corner:nom_ff_n40C_1v95	0
58	timing__setup__wns__corner:nom_ff_n40C_1v95	0.0
59	timing__hold_vio__count__corner:nom_ff_n40C_1v95	0
60	timing__hold_r2r__ws__corner:nom_ff_n40C_1v95	0.587006
61	timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95	0
62	timing__setup_vio__count__corner:nom_ff_n40C_1v95	0
63	timing__setup_r2r__ws__corner:nom_ff_n40C_1v95	Infinity
64	timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95	0
65	design__max_slew_violation__count	192
66	design__max_fanout_violation__count	14
67	design__max_cap_violation__count	1
68	clock__skew__worst_hold	-2.094480648201511
69	clock__skew__worst_setup	3.0075507380263278
70	timing__hold__ws	0.24338487469856057
71	timing__setup__ws	2.391910737178117
72	timing__hold__tns	0.0
73	timing__setup__tns	0.0
74	timing__hold__wns	0
75	timing__setup__wns	0.0
76	timing__hold_vio__count	0
77	timing__hold_r2r__ws	0.571341
78	timing__hold_r2r_vio__count	0
79	timing__setup_vio__count	0
80	timing__setup_r2r__ws	inf
81	timing__setup_r2r_vio__count	0
82	design__die__bbox	0.0 0.0 2800.0 1760.0
83	design__core__bbox	5.52 10.88 2794.04 1748.96
84	design__io	543
85	design__die__area	4.928E+6
86	design__core__area	4.84667E+6
87	design__instance__count__stdcell	70590
88	design__instance__area__stdcell	95369
89	design__instance__count__macros	0
90	design__instance__area__macros	0
91	design__instance__utilization	0.0196772
92	design__instance__utilization__stdcell	0.0196772
93	design__instance__count__class:buffer	32
94	design__instance__count__class:inverter	7
95	design__instance__count__class:sequential_cell	33
96	design__instance__count__class:multi_input_combinational_cell	273
97	flow__warnings__count	1
98	flow__errors__count	0
99	design__instance__count__class:fill_cell	485362
100	design__instance__count__class:tap_cell	69228
101	design__power_grid_violation__count__net:vccd1	0
102	design__power_grid_violation__count__net:vssd1	0
103	design__power_grid_violation__count	0
104	timing__drv__floating__nets	0
105	timing__drv__floating__pins	0
106	design__instance__displacement__total	0
107	design__instance__displacement__mean	0
108	design__instance__displacement__max	0
109	route__wirelength__estimated	101712
110	design__violations	0
111	design__instance__count__class:timing_repair_buffer	362
112	design__instance__count__class:clock_buffer	11
113	design__instance__count__setup_buffer	0
114	design__instance__count__hold_buffer	0
115	antenna__violating__nets	4
116	antenna__violating__pins	4
117	route__antenna_violation__count	4
118	design__instance__count__class:antenna_cell	644
119	antenna_diodes_count	2
120	route__net	1060
121	route__net__special	2
122	route__drc_errors__iter:1	198
123	route__wirelength__iter:1	102911
124	route__drc_errors__iter:2	82
125	route__wirelength__iter:2	102825
126	route__drc_errors__iter:3	84
127	route__wirelength__iter:3	102834
128	route__drc_errors__iter:4	5
129	route__wirelength__iter:4	102805
130	route__drc_errors__iter:5	0
131	route__wirelength__iter:5	102803
132	route__drc_errors	0
133	route__wirelength	102803
134	route__vias	4853
135	route__vias__singlecut	4853
136	route__vias__multicut	0
137	design__disconnected_pin__count	286
138	design__critical_disconnected_pin__count	0
139	route__wirelength__max	3004.91
140	timing__unannotated_net__count__corner:nom_tt_025C_1v80	420
141	timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80	0
142	timing__unannotated_net__count__corner:nom_ss_100C_1v60	420
143	timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60	0
144	timing__unannotated_net__count__corner:nom_ff_n40C_1v95	420
145	timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95	0
146	design__max_slew_violation__count__corner:min_tt_025C_1v80	0
147	design__max_fanout_violation__count__corner:min_tt_025C_1v80	14
148	design__max_cap_violation__count__corner:min_tt_025C_1v80	0
149	clock__skew__worst_hold__corner:min_tt_025C_1v80	-2.0946271976449062
150	clock__skew__worst_setup__corner:min_tt_025C_1v80	3.166766494223121
151	timing__hold__ws__corner:min_tt_025C_1v80	0.4132969639063154
152	timing__setup__ws__corner:min_tt_025C_1v80	7.087754583861198
153	timing__hold__tns__corner:min_tt_025C_1v80	0.0
154	timing__setup__tns__corner:min_tt_025C_1v80	0.0
155	timing__hold__wns__corner:min_tt_025C_1v80	0
156	timing__setup__wns__corner:min_tt_025C_1v80	0.0
157	timing__hold_vio__count__corner:min_tt_025C_1v80	0
158	timing__hold_r2r__ws__corner:min_tt_025C_1v80	0.992008
159	timing__hold_r2r_vio__count__corner:min_tt_025C_1v80	0
160	timing__setup_vio__count__corner:min_tt_025C_1v80	0
161	timing__setup_r2r__ws__corner:min_tt_025C_1v80	Infinity
162	timing__setup_r2r_vio__count__corner:min_tt_025C_1v80	0
163	timing__unannotated_net__count__corner:min_tt_025C_1v80	420
164	timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80	0
165	design__max_slew_violation__count__corner:min_ss_100C_1v60	120
166	design__max_fanout_violation__count__corner:min_ss_100C_1v60	14
167	design__max_cap_violation__count__corner:min_ss_100C_1v60	0
168	clock__skew__worst_hold__corner:min_ss_100C_1v60	-2.095250254823947
169	clock__skew__worst_setup__corner:min_ss_100C_1v60	3.037091553101025
170	timing__hold__ws__corner:min_ss_100C_1v60	1.141694771038144
171	timing__setup__ws__corner:min_ss_100C_1v60	2.494424293279187
172	timing__hold__tns__corner:min_ss_100C_1v60	0.0
173	timing__setup__tns__corner:min_ss_100C_1v60	0.0
174	timing__hold__wns__corner:min_ss_100C_1v60	0
175	timing__setup__wns__corner:min_ss_100C_1v60	0.0
176	timing__hold_vio__count__corner:min_ss_100C_1v60	0
177	timing__hold_r2r__ws__corner:min_ss_100C_1v60	2.180077
178	timing__hold_r2r_vio__count__corner:min_ss_100C_1v60	0
179	timing__setup_vio__count__corner:min_ss_100C_1v60	0
180	timing__setup_r2r__ws__corner:min_ss_100C_1v60	Infinity
181	timing__setup_r2r_vio__count__corner:min_ss_100C_1v60	0
182	timing__unannotated_net__count__corner:min_ss_100C_1v60	420
183	timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60	0
184	design__max_slew_violation__count__corner:min_ff_n40C_1v95	0
185	design__max_fanout_violation__count__corner:min_ff_n40C_1v95	14
186	design__max_cap_violation__count__corner:min_ff_n40C_1v95	0
187	clock__skew__worst_hold__corner:min_ff_n40C_1v95	-2.094480648201511
188	clock__skew__worst_setup__corner:min_ff_n40C_1v95	3.2570613794588086
189	timing__hold__ws__corner:min_ff_n40C_1v95	0.3001150524152958
190	timing__setup__ws__corner:min_ff_n40C_1v95	8.453670003294032
191	timing__hold__tns__corner:min_ff_n40C_1v95	0.0
192	timing__setup__tns__corner:min_ff_n40C_1v95	0.0
193	timing__hold__wns__corner:min_ff_n40C_1v95	0
194	timing__setup__wns__corner:min_ff_n40C_1v95	0.0
195	timing__hold_vio__count__corner:min_ff_n40C_1v95	0
196	timing__hold_r2r__ws__corner:min_ff_n40C_1v95	0.571341
197	timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95	0
198	timing__setup_vio__count__corner:min_ff_n40C_1v95	0
199	timing__setup_r2r__ws__corner:min_ff_n40C_1v95	Infinity
200	timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95	0
201	timing__unannotated_net__count__corner:min_ff_n40C_1v95	420
202	timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95	0
203	design__max_slew_violation__count__corner:max_tt_025C_1v80	12
204	design__max_fanout_violation__count__corner:max_tt_025C_1v80	14
205	design__max_cap_violation__count__corner:max_tt_025C_1v80	0
206	clock__skew__worst_hold__corner:max_tt_025C_1v80	-2.1012268075791374
207	clock__skew__worst_setup__corner:max_tt_025C_1v80	3.160448436855897
208	timing__hold__ws__corner:max_tt_025C_1v80	0.3314753010342061
209	timing__setup__ws__corner:max_tt_025C_1v80	7.0523784364040365
210	timing__hold__tns__corner:max_tt_025C_1v80	0.0
211	timing__setup__tns__corner:max_tt_025C_1v80	0.0
212	timing__hold__wns__corner:max_tt_025C_1v80	0
213	timing__setup__wns__corner:max_tt_025C_1v80	0.0
214	timing__hold_vio__count__corner:max_tt_025C_1v80	0
215	timing__hold_r2r__ws__corner:max_tt_025C_1v80	1.026777
216	timing__hold_r2r_vio__count__corner:max_tt_025C_1v80	0
217	timing__setup_vio__count__corner:max_tt_025C_1v80	0
218	timing__setup_r2r__ws__corner:max_tt_025C_1v80	Infinity
219	timing__setup_r2r_vio__count__corner:max_tt_025C_1v80	0
220	timing__unannotated_net__count__corner:max_tt_025C_1v80	420
221	timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80	0
222	design__max_slew_violation__count__corner:max_ss_100C_1v60	192
223	design__max_fanout_violation__count__corner:max_ss_100C_1v60	14
224	design__max_cap_violation__count__corner:max_ss_100C_1v60	1
225	clock__skew__worst_hold__corner:max_ss_100C_1v60	-2.101982647435679
226	clock__skew__worst_setup__corner:max_ss_100C_1v60	3.0075507380263278
227	timing__hold__ws__corner:max_ss_100C_1v60	1.0005818679036624
228	timing__setup__ws__corner:max_ss_100C_1v60	2.391910737178117
229	timing__hold__tns__corner:max_ss_100C_1v60	0.0
230	timing__setup__tns__corner:max_ss_100C_1v60	0.0
231	timing__hold__wns__corner:max_ss_100C_1v60	0
232	timing__setup__wns__corner:max_ss_100C_1v60	0.0
233	timing__hold_vio__count__corner:max_ss_100C_1v60	0
234	timing__hold_r2r__ws__corner:max_ss_100C_1v60	2.250683
235	timing__hold_r2r_vio__count__corner:max_ss_100C_1v60	0
236	timing__setup_vio__count__corner:max_ss_100C_1v60	0
237	timing__setup_r2r__ws__corner:max_ss_100C_1v60	Infinity
238	timing__setup_r2r_vio__count__corner:max_ss_100C_1v60	0
239	timing__unannotated_net__count__corner:max_ss_100C_1v60	420
240	timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60	0
241	design__max_slew_violation__count__corner:max_ff_n40C_1v95	0
242	design__max_fanout_violation__count__corner:max_ff_n40C_1v95	14
243	design__max_cap_violation__count__corner:max_ff_n40C_1v95	0
244	clock__skew__worst_hold__corner:max_ff_n40C_1v95	-2.1008075873531826
245	clock__skew__worst_setup__corner:max_ff_n40C_1v95	3.259567374940867
246	timing__hold__ws__corner:max_ff_n40C_1v95	0.24338487469856057
247	timing__setup__ws__corner:max_ff_n40C_1v95	8.420825164404606
248	timing__hold__tns__corner:max_ff_n40C_1v95	0.0
249	timing__setup__tns__corner:max_ff_n40C_1v95	0.0
250	timing__hold__wns__corner:max_ff_n40C_1v95	0
251	timing__setup__wns__corner:max_ff_n40C_1v95	0.0
252	timing__hold_vio__count__corner:max_ff_n40C_1v95	0
253	timing__hold_r2r__ws__corner:max_ff_n40C_1v95	0.591791
254	timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95	0
255	timing__setup_vio__count__corner:max_ff_n40C_1v95	0
256	timing__setup_r2r__ws__corner:max_ff_n40C_1v95	Infinity
257	timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95	0
258	timing__unannotated_net__count__corner:max_ff_n40C_1v95	420
259	timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95	0
260	timing__unannotated_net__count	420
261	timing__unannotated_net_filtered__count	0
262	design_powergrid__voltage__worst__net:vccd1__corner:nom_tt_025C_1v80	1.79983
263	design_powergrid__drop__average__net:vccd1__corner:nom_tt_025C_1v80	1.8
264	design_powergrid__drop__worst__net:vccd1__corner:nom_tt_025C_1v80	0.000166719
265	design_powergrid__voltage__worst__net:vssd1__corner:nom_tt_025C_1v80	0.000205177
266	design_powergrid__drop__average__net:vssd1__corner:nom_tt_025C_1v80	2.51703E-7
267	design_powergrid__drop__worst__net:vssd1__corner:nom_tt_025C_1v80	0.000205177
268	design_powergrid__voltage__worst	0.000205177
269	design_powergrid__voltage__worst__net:vccd1	1.79983
270	design_powergrid__drop__worst	0.000205177
271	design_powergrid__drop__worst__net:vccd1	0.000166719
272	design_powergrid__voltage__worst__net:vssd1	0.000205177
273	design_powergrid__drop__worst__net:vssd1	0.000205177
274	ir__voltage__worst	1.8000000000000000444089209850062616169452667236328125
275	ir__drop__avg	2.30999999999999990605605015847601180212222971022129058837890625E-7
276	ir__drop__worst	0.0001669999999999999935017258589908806243329308927059173583984375
277	design__xor_difference__count	0
278	magic__drc_error__count	0
279	klayout__drc_error__count	0
280	magic__illegal_overlap__count	0
281	design__lvs_device_difference__count	0
282	design__lvs_net_difference__count	0
283	design__lvs_property_fail__count	0
284	design__lvs_error__count	0
285	design__lvs_unmatched_device__count	0
286	design__lvs_unmatched_net__count	0
287	design__lvs_unmatched_pin__count	0