cah f2e419e25d fix: flatten LLR interface to packed vector for Yosys compatibility ...

Yosys doesn't support unpacked array ports. Changed llr_in/llr_input
from `logic signed [Q-1:0] llr[N]` to `logic [N*Q-1:0] llr` packed
vector. Also fixed blocking assignment in INIT loops (Verilator
BLKLOOPINIT requirement).

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-02-25 21:07:29 -07:00

4.9 KiB

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