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Update RTL base matrix to match working Python model

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IRA staircase structure: col 0 = info (dv=7), cols 1-7 = parity (dv=1-2).
RTL decoder core still needs CN update rework for variable degree.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
cah
2026-02-23 21:56:48 -07:00
parent b7b76da46e
commit 18333e32f5
1 changed files with 38 additions and 35 deletions
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73
rtl/ldpc_decoder_core.sv
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@@ -48,46 +48,49 @@ module ldpc_decoder_core #(
// H_BASE[row][col] = cyclic shift amount, or -1 if zero sub-matrix
// =========================================================================
// This is a placeholder base matrix for rate-1/8 QC-LDPC.
// Must be replaced with a properly designed matrix (PEG algorithm or
// density evolution optimized). All entries >= 0 means fully connected
// (regular dv=7, dc=8). For irregular codes, some entries would be -1.
// IRA staircase base matrix for rate-1/8 QC-LDPC
// Column 0 = info (dv=7), Columns 1-7 = parity with lower-triangular staircase
// This matches model/ldpc_sim.py exactly.
//
// TODO: Replace with optimized base matrix from model/design_h_matrix.py
// Row 0: info(0) + p1(5)
// Row 1: info(11) + p1(3) + p2(0)
// Row 2: info(17) + p2(7) + p3(0)
// Row 3: info(23) + p3(13) + p4(0)
// Row 4: info(29) + p4(19) + p5(0)
// Row 5: info(3) + p5(25) + p6(0)
// Row 6: info(9) + p6(31) + p7(0)
logic signed [5:0] H_BASE [M_BASE][N_BASE];
// Shift values for 7x8 base matrix (Z=32, values 0..31, -1=null)
// This is a regular (7,8) code - every entry is connected
initial begin
// Row 0
H_BASE[0][0] = 0; H_BASE[0][1] = 5; H_BASE[0][2] = 11;
H_BASE[0][3] = 17; H_BASE[0][4] = 23; H_BASE[0][5] = 29;
H_BASE[0][6] = 3; H_BASE[0][7] = 9;
// Row 1
H_BASE[1][0] = 15; H_BASE[1][1] = 0; H_BASE[1][2] = 21;
H_BASE[1][3] = 7; H_BASE[1][4] = 13; H_BASE[1][5] = 19;
H_BASE[1][6] = 25; H_BASE[1][7] = 31;
// Row 2
H_BASE[2][0] = 10; H_BASE[2][1] = 20; H_BASE[2][2] = 0;
H_BASE[2][3] = 30; H_BASE[2][4] = 8; H_BASE[2][5] = 16;
H_BASE[2][6] = 24; H_BASE[2][7] = 2;
// Row 3
H_BASE[3][0] = 27; H_BASE[3][1] = 14; H_BASE[3][2] = 1;
H_BASE[3][3] = 0; H_BASE[3][4] = 18; H_BASE[3][5] = 6;
H_BASE[3][6] = 12; H_BASE[3][7] = 22;
// Row 4
H_BASE[4][0] = 4; H_BASE[4][1] = 28; H_BASE[4][2] = 16;
H_BASE[4][3] = 12; H_BASE[4][4] = 0; H_BASE[4][5] = 26;
H_BASE[4][6] = 8; H_BASE[4][7] = 20;
// Row 5
H_BASE[5][0] = 19; H_BASE[5][1] = 9; H_BASE[5][2] = 31;
H_BASE[5][3] = 25; H_BASE[5][4] = 15; H_BASE[5][5] = 0;
H_BASE[5][6] = 21; H_BASE[5][7] = 11;
// Row 6
H_BASE[6][0] = 22; H_BASE[6][1] = 26; H_BASE[6][2] = 6;
H_BASE[6][3] = 14; H_BASE[6][4] = 30; H_BASE[6][5] = 10;
H_BASE[6][6] = 0; H_BASE[6][7] = 18;
// Row 0: cols 0,1 connected
H_BASE[0][0] = 0; H_BASE[0][1] = 5; H_BASE[0][2] = -1;
H_BASE[0][3] = -1; H_BASE[0][4] = -1; H_BASE[0][5] = -1;
H_BASE[0][6] = -1; H_BASE[0][7] = -1;
// Row 1: cols 0,1,2 connected
H_BASE[1][0] = 11; H_BASE[1][1] = 3; H_BASE[1][2] = 0;
H_BASE[1][3] = -1; H_BASE[1][4] = -1; H_BASE[1][5] = -1;
H_BASE[1][6] = -1; H_BASE[1][7] = -1;
// Row 2: cols 0,2,3 connected
H_BASE[2][0] = 17; H_BASE[2][1] = -1; H_BASE[2][2] = 7;
H_BASE[2][3] = 0; H_BASE[2][4] = -1; H_BASE[2][5] = -1;
H_BASE[2][6] = -1; H_BASE[2][7] = -1;
// Row 3: cols 0,3,4 connected
H_BASE[3][0] = 23; H_BASE[3][1] = -1; H_BASE[3][2] = -1;
H_BASE[3][3] = 13; H_BASE[3][4] = 0; H_BASE[3][5] = -1;
H_BASE[3][6] = -1; H_BASE[3][7] = -1;
// Row 4: cols 0,4,5 connected
H_BASE[4][0] = 29; H_BASE[4][1] = -1; H_BASE[4][2] = -1;
H_BASE[4][3] = -1; H_BASE[4][4] = 19; H_BASE[4][5] = 0;
H_BASE[4][6] = -1; H_BASE[4][7] = -1;
// Row 5: cols 0,5,6 connected
H_BASE[5][0] = 3; H_BASE[5][1] = -1; H_BASE[5][2] = -1;
H_BASE[5][3] = -1; H_BASE[5][4] = -1; H_BASE[5][5] = 25;
H_BASE[5][6] = 0; H_BASE[5][7] = -1;
// Row 6: cols 0,6,7 connected
H_BASE[6][0] = 9; H_BASE[6][1] = -1; H_BASE[6][2] = -1;
H_BASE[6][3] = -1; H_BASE[6][4] = -1; H_BASE[6][5] = -1;
H_BASE[6][6] = 31; H_BASE[6][7] = 0;
end
// =========================================================================