test: add standalone Verilator testbench for LDPC decoder

Add tb/tb_ldpc_decoder.sv with Wishbone read/write tasks, version
register test, and all-zero codeword decode test. Add tb/Makefile
with lint and sim targets.

Fix two RTL bugs found during testbench bring-up:
- ldpc_decoder_core.sv: skip unconnected H_BASE columns (shift=-1)
  in LAYER_READ, LAYER_WRITE, and SYNDROME states to prevent
  out-of-bounds array access and belief corruption
- ldpc_decoder_core.sv: fix syndrome_ok timing race by adding
  SYNDROME_DONE state so the registered result is available before
  the early-termination decision
- wishbone_interface.sv: fix VERSION_ID typo (0xLD01 -> 0x1D01)

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

rtl/wishbone_interface.sv

@@ -40,7 +40,7 @@ module wishbone_interface #(
     output logic                    irq_o
 );
 
-    localparam VERSION_ID = 32'hLD01_0001;  // LDPC v0.1 build 1
+    localparam VERSION_ID = 32'h1D01_0001;  // LDPC v0.1 build 1
 
     // Wishbone handshake: ack on valid cycle
     logic wb_valid;