test: add standalone Verilator testbench for LDPC decoder

Add tb/tb_ldpc_decoder.sv with Wishbone read/write tasks, version
register test, and all-zero codeword decode test. Add tb/Makefile
with lint and sim targets.

Fix two RTL bugs found during testbench bring-up:
- ldpc_decoder_core.sv: skip unconnected H_BASE columns (shift=-1)
  in LAYER_READ, LAYER_WRITE, and SYNDROME states to prevent
  out-of-bounds array access and belief corruption
- ldpc_decoder_core.sv: fix syndrome_ok timing race by adding
  SYNDROME_DONE state so the registered result is available before
  the early-termination decision
- wishbone_interface.sv: fix VERSION_ID typo (0xLD01 -> 0x1D01)

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

tb/Makefile

@@ -0,0 +1,28 @@
+RTL_DIR = ../rtl
+RTL_FILES = $(RTL_DIR)/ldpc_decoder_top.sv \
+            $(RTL_DIR)/ldpc_decoder_core.sv \
+            $(RTL_DIR)/wishbone_interface.sv
+
+.PHONY: lint sim clean
+
+lint:
+	verilator --lint-only -Wall \
+		-Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-CASEINCOMPLETE \
+		-Wno-BLKSEQ -Wno-BLKLOOPINIT -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM \
+		--unroll-count 1024 \
+		$(RTL_FILES) --top-module ldpc_decoder_top
+
+sim: obj_dir/Vtb_ldpc_decoder
+	./obj_dir/Vtb_ldpc_decoder
+
+obj_dir/Vtb_ldpc_decoder: tb_ldpc_decoder.sv $(RTL_FILES)
+	verilator --binary --timing --trace \
+		-o Vtb_ldpc_decoder \
+		-Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-CASEINCOMPLETE \
+		-Wno-BLKSEQ -Wno-BLKLOOPINIT -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM \
+		--unroll-count 1024 \
+		tb_ldpc_decoder.sv $(RTL_FILES) \
+		--top-module tb_ldpc_decoder
+
+clean:
+	rm -rf obj_dir *.vcd