test: add vector-driven Verilator testbench with Python model cross-check

Add gen_verilator_vectors.py to convert test_vectors.json into hex files
for $readmemh, and tb_ldpc_vectors.sv to drive 20 test vectors through
the RTL decoder and verify bit-exact matching against the Python model.

All 11 converged vectors pass with exact decoded word, convergence flag,
and zero syndrome weight. All 9 non-converged vectors match the Python
model's decoded word, iteration count, and syndrome weight exactly.

Three RTL bugs fixed in ldpc_decoder_core.sv during testing:
- Magnitude overflow: -32 (6'b100000) negation overflowed 5-bit field
  to 0; now clamped to max magnitude 31
- Converged flag persistence: moved clearing from IDLE to INIT so host
  can read results after decode completes
- msg_cn2vn zeroing: bypass stale array reads on first iteration
  (iter_cnt==0) to avoid Verilator scheduling issues with large 3D
  array initialization

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

tb/Makefile

@@ -3,7 +3,7 @@ RTL_FILES = $(RTL_DIR)/ldpc_decoder_top.sv \
             $(RTL_DIR)/ldpc_decoder_core.sv \
             $(RTL_DIR)/wishbone_interface.sv
 
-.PHONY: lint sim clean
+.PHONY: lint sim sim_vectors clean
 
 lint:
 	verilator --lint-only -Wall \
@@ -24,5 +24,17 @@ obj_dir/Vtb_ldpc_decoder: tb_ldpc_decoder.sv $(RTL_FILES)
 		tb_ldpc_decoder.sv $(RTL_FILES) \
 		--top-module tb_ldpc_decoder
 
+sim_vectors: obj_dir/Vtb_ldpc_vectors
+	./obj_dir/Vtb_ldpc_vectors
+
+obj_dir/Vtb_ldpc_vectors: tb_ldpc_vectors.sv $(RTL_FILES)
+	verilator --binary --timing --trace \
+		-o Vtb_ldpc_vectors \
+		-Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-CASEINCOMPLETE \
+		-Wno-BLKSEQ -Wno-BLKLOOPINIT -Wno-UNUSEDSIGNAL -Wno-UNUSEDPARAM \
+		--unroll-count 1024 \
+		tb_ldpc_vectors.sv $(RTL_FILES) \
+		--top-module tb_ldpc_vectors
+
 clean:
 	rm -rf obj_dir *.vcd