fix: RTL bugs in decoder core + add standalone Verilator testbench

RTL fixes:
- Skip unconnected columns (H_BASE=-1) in LAYER_READ/WRITE/SYNDROME
- Set unconnected VN->CN messages to +MAX (not 0) to avoid
  corrupting min-sum minimum computation
- Add SYNDROME_DONE state to fix timing race on syndrome_ok
- Fix VERSION_ID hex literal (0xLD01 -> 0x1D01)

Testbench verifies VERSION register read and clean all-zero decode.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

rtl/ldpc_decoder_core.sv

@@ -241,9 +241,9 @@ module ldpc_decoder_core #(
                             vn_to_cn[col_idx][z] <= sat_sub(belief_val, old_msg);
                         end
                     end else begin
-                        // Unconnected: set VN->CN messages to 0
+                        // Unconnected: set to +MAX so magnitude doesn't affect min-sum
                         for (int z = 0; z < Z; z++)
-                            vn_to_cn[col_idx][z] <= '0;
+                            vn_to_cn[col_idx][z] <= {1'b0, {(Q-1){1'b1}}};  // +31
                     end
 
                     if (col_idx == N_BASE - 1)