Initial LDPC optical decoder project scaffold
Rate-1/8 QC-LDPC decoder for photon-starved optical communication. Target: Efabless chipIgnite (SkyWater 130nm, Caravel harness). - RTL: decoder top, core (layered min-sum), Wishbone interface - Python behavioral model with Poisson channel simulation - 7x8 base matrix, Z=32, n=256, k=32 Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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CLAUDE.md
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# ldpc_optical - LDPC Decoder for Photon-Starved Optical Communication
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## Overview
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Low-Density Parity Check (LDPC) decoder targeting the Efabless chipIgnite program (SkyWater 130nm, Caravel harness). Designed for photon-starved optical communication links where received signals are soft probabilities (partial bits), not hard 0/1 decisions.
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## Target Application
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- **Channel**: Photon-counting optical (Poisson channel, single-photon detectors)
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- **Use case**: Deep space optical, underwater optical, or any photon-starved link
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- **Input format**: Soft LLR (log-likelihood ratios) representing probability of 0 vs 1
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- **Code rate**: 1/8 (32 info bits -> 256 coded bits) for maximum coding gain
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- **Decoding**: Offset min-sum (hardware-friendly approximation of belief propagation)
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## Architecture
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```
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Caravel SoC (Sky130, ~10 mm^2 user area)
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+==============================================+
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| PicoRV32 (Caravel) |
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| | |
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| | Wishbone B4 |
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| | |
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| +---v--------------------------------------+|
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| | ldpc_decoder_top ||
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| | | ||
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| | +-- wishbone_interface ||
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| | +-- llr_ram (256 x 6-bit) ||
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| | +-- msg_ram (1792 x 6-bit) ||
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| | +-- vn_update_array [Z=32] ||
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| | +-- cn_update_array [Z=32] ||
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| | +-- barrel_shifter_z32 ||
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| | +-- iteration_controller ||
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| | +-- syndrome_checker ||
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| | +-- hard_decision_out ||
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| +------------------------------------------+|
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+==============================================+
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```
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## Code Parameters
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| Parameter | Value | Notes |
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|-----------|-------|-------|
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| Code type | QC-LDPC | Quasi-cyclic for hardware efficiency |
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| Rate | 1/8 (R = 0.125) | k=32 info bits, n=256 coded bits |
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| Base matrix | 7 x 8 | M_BASE=7 rows, N_BASE=8 cols |
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| Lifting factor Z | 32 | n = N_BASE * Z = 256 |
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| Quantization | 6-bit signed | 1 sign + 5 magnitude |
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| Max iterations | 30 | With early termination on syndrome check |
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| Decoding algorithm | Offset min-sum | Offset ~0.5, ~0.2 dB from sum-product |
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| Scheduling | Layered (row-serial) | ~2x faster convergence than flooding |
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## Fabrication Target
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| Parameter | Value |
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|-----------|-------|
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| Process | SkyWater 130nm (Sky130) |
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| Platform | Efabless Caravel harness |
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| User area | ~10.3 mm^2 (2.92 x 3.52 mm) |
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| Target clock | 150 MHz (aggressive for Sky130) |
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| Estimated area | ~1.5 mm^2 (decoder only) |
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| Interface | Wishbone B4 slave |
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## Directory Structure
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- `rtl/` - SystemVerilog RTL sources
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- `tb/` - Verilator testbenches
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- `model/` - Python behavioral model (bit-exact reference)
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- `data/` - H-matrix definitions, test vectors
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- `openlane/` - OpenLane ASIC flow configuration (future)
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- `docs/` - Design documentation
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## Channel Model (Photon-Counting Optical)
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The receiver uses single-photon detectors. Each time slot produces a photon count (or binary click/no-click). The channel LLR is:
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```
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LLR(y) = log(P(y | bit=1) / P(y | bit=0))
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```
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For binary detection (click/no-click):
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- P(click | bit=1) = 1 - exp(-(lambda_s + lambda_b))
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- P(click | bit=0) = 1 - exp(-lambda_b)
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where lambda_s = signal photons/slot, lambda_b = background photons/slot.
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LLR computation is done in software (PicoRV32). The decoder only sees quantized 6-bit LLRs.
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## Simulation
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```bash
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# Verilator lint check
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verilator --lint-only -Wall rtl/*.sv
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# Run testbench
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verilator --binary --timing -o sim_ldpc tb/tb_ldpc_decoder.sv rtl/*.sv
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./obj_dir/sim_ldpc
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# Python behavioral model
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cd model && python3 ldpc_sim.py
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```
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## Key Design Decisions
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1. **Soft input (LLR), not hard bits**: The whole point of LDPC for photon-starved channels. Hard-decision decoding would lose ~2-3 dB of coding gain.
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2. **Rate 1/8**: Extreme redundancy for very low SNR. Shannon limit at R=1/8 is Eb/N0 ~ -1.59 dB; practical LDPC can approach 0 to +1 dB.
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3. **Min-sum over sum-product**: No multipliers or LUT-based tanh needed. Just comparators and adders. Critical for area on Sky130.
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4. **Layered scheduling**: Process one row of base matrix at a time, updating messages immediately. Converges in ~half the iterations of flooding schedule.
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5. **Z=32 parallelism**: 32 VN/CN processors working in parallel. Matches lifting factor for natural throughput.
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## Performance Estimates
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- Codeword decode: ~630 cycles (30 iterations x 21 cycles/iter)
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- At 150 MHz: ~238K codewords/sec
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- Decoded throughput: 238K x 32 bits = 7.6 Mbps
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- Latency: ~4.2 us per codeword
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- Area: ~1.5 mm^2 at Sky130 (leaves ~8.5 mm^2 for additional blocks)
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## Register Map (Wishbone, word-addressed)
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| Offset | Name | R/W | Description |
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|--------|------|-----|-------------|
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| 0x00 | CTRL | R/W | [0]=start, [1]=early_term_en, [12:8]=max_iter |
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| 0x04 | STATUS | R | [0]=busy, [1]=converged, [12:8]=iterations_used |
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| 0x08 | CONFIG | R/W | [2:0]=code_sel (future: multiple H matrices) |
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| 0x10-0x4F | LLR_IN | W | Channel LLRs, packed 5x6-bit per word |
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| 0x50-0x57 | DECODED | R | 32 decoded bits (1 word) |
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| 0x5C | SYNDROME_WT | R | Syndrome weight (0 = valid codeword) |
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## Notes
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- No multipliers in the entire design (add/compare/select only)
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- 150 MHz is aggressive for Sky130 — may need to relax to 100 MHz depending on synthesis results
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- Error floor at rate 1/8 expected around BER 10^-7 to 10^-9 — may need outer RS code for optical comm BER requirements
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- Base matrix H must be carefully designed (PEG algorithm or density evolution optimization)
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