cah b7449a6191 fix: RTL bugs in decoder core + add standalone Verilator testbench ...

RTL fixes:
- Skip unconnected columns (H_BASE=-1) in LAYER_READ/WRITE/SYNDROME
- Set unconnected VN->CN messages to +MAX (not 0) to avoid
  corrupting min-sum minimum computation
- Add SYNDROME_DONE state to fix timing race on syndrome_ok
- Fix VERSION_ID hex literal (0xLD01 -> 0x1D01)

Testbench verifies VERSION register read and clean all-zero decode.

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

2026-02-25 19:05:52 -07:00

..

ldpc_decoder_core.sv

fix: RTL bugs in decoder core + add standalone Verilator testbench

2026-02-25 19:05:52 -07:00

ldpc_decoder_top.sv

Initial LDPC optical decoder project scaffold

2026-02-23 21:47:40 -07:00

wishbone_interface.sv

test: add standalone Verilator testbench for LDPC decoder

2026-02-25 19:00:41 -07:00