13 KiB
13 KiB
| 1 | Metric | Value |
|---|---|---|
| 2 | design__lint_error__count | 0 |
| 3 | design__lint_timing_construct__count | 0 |
| 4 | design__lint_warning__count | 5 |
| 5 | design__inferred_latch__count | 0 |
| 6 | design__instance__count | 1 |
| 7 | design__instance_unmapped__count | 0 |
| 8 | synthesis__check_error__count | 0 |
| 9 | design__max_slew_violation__count__corner:nom_tt_025C_1v80 | 0 |
| 10 | design__max_fanout_violation__count__corner:nom_tt_025C_1v80 | 31 |
| 11 | design__max_cap_violation__count__corner:nom_tt_025C_1v80 | 0 |
| 12 | power__internal__total | 0.00019575921760406345 |
| 13 | power__switching__total | 0.00044556421926245093 |
| 14 | power__leakage__total | 1.919598524580124E-8 |
| 15 | power__total | 0.0006413426599465311 |
| 16 | clock__skew__worst_hold__corner:nom_tt_025C_1v80 | -2.096730848291461 |
| 17 | clock__skew__worst_setup__corner:nom_tt_025C_1v80 | 3.153387418219582 |
| 18 | timing__hold__ws__corner:nom_tt_025C_1v80 | 0.3479669983976151 |
| 19 | timing__setup__ws__corner:nom_tt_025C_1v80 | 7.060524809099921 |
| 20 | timing__hold__tns__corner:nom_tt_025C_1v80 | 0.0 |
| 21 | timing__setup__tns__corner:nom_tt_025C_1v80 | 0.0 |
| 22 | timing__hold__wns__corner:nom_tt_025C_1v80 | 0 |
| 23 | timing__setup__wns__corner:nom_tt_025C_1v80 | 0.0 |
| 24 | timing__hold_vio__count__corner:nom_tt_025C_1v80 | 0 |
| 25 | timing__hold_r2r__ws__corner:nom_tt_025C_1v80 | 1.019479 |
| 26 | timing__hold_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 |
| 27 | timing__setup_vio__count__corner:nom_tt_025C_1v80 | 0 |
| 28 | timing__setup_r2r__ws__corner:nom_tt_025C_1v80 | Infinity |
| 29 | timing__setup_r2r_vio__count__corner:nom_tt_025C_1v80 | 0 |
| 30 | design__max_slew_violation__count__corner:nom_ss_100C_1v60 | 4 |
| 31 | design__max_fanout_violation__count__corner:nom_ss_100C_1v60 | 31 |
| 32 | design__max_cap_violation__count__corner:nom_ss_100C_1v60 | 1 |
| 33 | clock__skew__worst_hold__corner:nom_ss_100C_1v60 | -2.0973783303777345 |
| 34 | clock__skew__worst_setup__corner:nom_ss_100C_1v60 | 3.0065613072387984 |
| 35 | timing__hold__ws__corner:nom_ss_100C_1v60 | 1.0254970496377398 |
| 36 | timing__setup__ws__corner:nom_ss_100C_1v60 | 2.424894131904935 |
| 37 | timing__hold__tns__corner:nom_ss_100C_1v60 | 0.0 |
| 38 | timing__setup__tns__corner:nom_ss_100C_1v60 | 0.0 |
| 39 | timing__hold__wns__corner:nom_ss_100C_1v60 | 0 |
| 40 | timing__setup__wns__corner:nom_ss_100C_1v60 | 0.0 |
| 41 | timing__hold_vio__count__corner:nom_ss_100C_1v60 | 0 |
| 42 | timing__hold_r2r__ws__corner:nom_ss_100C_1v60 | 2.235596 |
| 43 | timing__hold_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 |
| 44 | timing__setup_vio__count__corner:nom_ss_100C_1v60 | 0 |
| 45 | timing__setup_r2r__ws__corner:nom_ss_100C_1v60 | Infinity |
| 46 | timing__setup_r2r_vio__count__corner:nom_ss_100C_1v60 | 0 |
| 47 | design__max_slew_violation__count__corner:nom_ff_n40C_1v95 | 0 |
| 48 | design__max_fanout_violation__count__corner:nom_ff_n40C_1v95 | 31 |
| 49 | design__max_cap_violation__count__corner:nom_ff_n40C_1v95 | 0 |
| 50 | clock__skew__worst_hold__corner:nom_ff_n40C_1v95 | -2.0964635065795703 |
| 51 | clock__skew__worst_setup__corner:nom_ff_n40C_1v95 | 3.2516608104250833 |
| 52 | timing__hold__ws__corner:nom_ff_n40C_1v95 | 0.2570081997744249 |
| 53 | timing__setup__ws__corner:nom_ff_n40C_1v95 | 8.432016212809332 |
| 54 | timing__hold__tns__corner:nom_ff_n40C_1v95 | 0.0 |
| 55 | timing__setup__tns__corner:nom_ff_n40C_1v95 | 0.0 |
| 56 | timing__hold__wns__corner:nom_ff_n40C_1v95 | 0 |
| 57 | timing__setup__wns__corner:nom_ff_n40C_1v95 | 0.0 |
| 58 | timing__hold_vio__count__corner:nom_ff_n40C_1v95 | 0 |
| 59 | timing__hold_r2r__ws__corner:nom_ff_n40C_1v95 | 0.587006 |
| 60 | timing__hold_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 |
| 61 | timing__setup_vio__count__corner:nom_ff_n40C_1v95 | 0 |
| 62 | timing__setup_r2r__ws__corner:nom_ff_n40C_1v95 | Infinity |
| 63 | timing__setup_r2r_vio__count__corner:nom_ff_n40C_1v95 | 0 |
| 64 | design__max_slew_violation__count__corner:min_tt_025C_1v80 | 0 |
| 65 | design__max_fanout_violation__count__corner:min_tt_025C_1v80 | 31 |
| 66 | design__max_cap_violation__count__corner:min_tt_025C_1v80 | 0 |
| 67 | clock__skew__worst_hold__corner:min_tt_025C_1v80 | -2.0946271976449062 |
| 68 | clock__skew__worst_setup__corner:min_tt_025C_1v80 | 3.1658698780830754 |
| 69 | timing__hold__ws__corner:min_tt_025C_1v80 | 0.4135385484433063 |
| 70 | timing__setup__ws__corner:min_tt_025C_1v80 | 7.08808853895645 |
| 71 | timing__hold__tns__corner:min_tt_025C_1v80 | 0.0 |
| 72 | timing__setup__tns__corner:min_tt_025C_1v80 | 0.0 |
| 73 | timing__hold__wns__corner:min_tt_025C_1v80 | 0 |
| 74 | timing__setup__wns__corner:min_tt_025C_1v80 | 0.0 |
| 75 | timing__hold_vio__count__corner:min_tt_025C_1v80 | 0 |
| 76 | timing__hold_r2r__ws__corner:min_tt_025C_1v80 | 0.992008 |
| 77 | timing__hold_r2r_vio__count__corner:min_tt_025C_1v80 | 0 |
| 78 | timing__setup_vio__count__corner:min_tt_025C_1v80 | 0 |
| 79 | timing__setup_r2r__ws__corner:min_tt_025C_1v80 | Infinity |
| 80 | timing__setup_r2r_vio__count__corner:min_tt_025C_1v80 | 0 |
| 81 | design__max_slew_violation__count__corner:min_ss_100C_1v60 | 0 |
| 82 | design__max_fanout_violation__count__corner:min_ss_100C_1v60 | 31 |
| 83 | design__max_cap_violation__count__corner:min_ss_100C_1v60 | 0 |
| 84 | clock__skew__worst_hold__corner:min_ss_100C_1v60 | -2.0952484784670573 |
| 85 | clock__skew__worst_setup__corner:min_ss_100C_1v60 | 3.035826786995602 |
| 86 | timing__hold__ws__corner:min_ss_100C_1v60 | 1.14169033014592 |
| 87 | timing__setup__ws__corner:min_ss_100C_1v60 | 2.495028254621664 |
| 88 | timing__hold__tns__corner:min_ss_100C_1v60 | 0.0 |
| 89 | timing__setup__tns__corner:min_ss_100C_1v60 | 0.0 |
| 90 | timing__hold__wns__corner:min_ss_100C_1v60 | 0 |
| 91 | timing__setup__wns__corner:min_ss_100C_1v60 | 0.0 |
| 92 | timing__hold_vio__count__corner:min_ss_100C_1v60 | 0 |
| 93 | timing__hold_r2r__ws__corner:min_ss_100C_1v60 | 2.180078 |
| 94 | timing__hold_r2r_vio__count__corner:min_ss_100C_1v60 | 0 |
| 95 | timing__setup_vio__count__corner:min_ss_100C_1v60 | 0 |
| 96 | timing__setup_r2r__ws__corner:min_ss_100C_1v60 | Infinity |
| 97 | timing__setup_r2r_vio__count__corner:min_ss_100C_1v60 | 0 |
| 98 | design__max_slew_violation__count__corner:min_ff_n40C_1v95 | 0 |
| 99 | design__max_fanout_violation__count__corner:min_ff_n40C_1v95 | 31 |
| 100 | design__max_cap_violation__count__corner:min_ff_n40C_1v95 | 0 |
| 101 | clock__skew__worst_hold__corner:min_ff_n40C_1v95 | -2.094480648201511 |
| 102 | clock__skew__worst_setup__corner:min_ff_n40C_1v95 | 3.2563974660713058 |
| 103 | timing__hold__ws__corner:min_ff_n40C_1v95 | 0.3004605538303306 |
| 104 | timing__setup__ws__corner:min_ff_n40C_1v95 | 8.453748162997176 |
| 105 | timing__hold__tns__corner:min_ff_n40C_1v95 | 0.0 |
| 106 | timing__setup__tns__corner:min_ff_n40C_1v95 | 0.0 |
| 107 | timing__hold__wns__corner:min_ff_n40C_1v95 | 0 |
| 108 | timing__setup__wns__corner:min_ff_n40C_1v95 | 0.0 |
| 109 | timing__hold_vio__count__corner:min_ff_n40C_1v95 | 0 |
| 110 | timing__hold_r2r__ws__corner:min_ff_n40C_1v95 | 0.571340 |
| 111 | timing__hold_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 |
| 112 | timing__setup_vio__count__corner:min_ff_n40C_1v95 | 0 |
| 113 | timing__setup_r2r__ws__corner:min_ff_n40C_1v95 | Infinity |
| 114 | timing__setup_r2r_vio__count__corner:min_ff_n40C_1v95 | 0 |
| 115 | design__max_slew_violation__count__corner:max_tt_025C_1v80 | 0 |
| 116 | design__max_fanout_violation__count__corner:max_tt_025C_1v80 | 31 |
| 117 | design__max_cap_violation__count__corner:max_tt_025C_1v80 | 0 |
| 118 | clock__skew__worst_hold__corner:max_tt_025C_1v80 | -2.1012276957575824 |
| 119 | clock__skew__worst_setup__corner:max_tt_025C_1v80 | 3.1584722398161738 |
| 120 | timing__hold__ws__corner:max_tt_025C_1v80 | 0.33149040006776803 |
| 121 | timing__setup__ws__corner:max_tt_025C_1v80 | 7.0531102954425675 |
| 122 | timing__hold__tns__corner:max_tt_025C_1v80 | 0.0 |
| 123 | timing__setup__tns__corner:max_tt_025C_1v80 | 0.0 |
| 124 | timing__hold__wns__corner:max_tt_025C_1v80 | 0 |
| 125 | timing__setup__wns__corner:max_tt_025C_1v80 | 0.0 |
| 126 | timing__hold_vio__count__corner:max_tt_025C_1v80 | 0 |
| 127 | timing__hold_r2r__ws__corner:max_tt_025C_1v80 | 1.026777 |
| 128 | timing__hold_r2r_vio__count__corner:max_tt_025C_1v80 | 0 |
| 129 | timing__setup_vio__count__corner:max_tt_025C_1v80 | 0 |
| 130 | timing__setup_r2r__ws__corner:max_tt_025C_1v80 | Infinity |
| 131 | timing__setup_r2r_vio__count__corner:max_tt_025C_1v80 | 0 |
| 132 | design__max_slew_violation__count__corner:max_ss_100C_1v60 | 4 |
| 133 | design__max_fanout_violation__count__corner:max_ss_100C_1v60 | 31 |
| 134 | design__max_cap_violation__count__corner:max_ss_100C_1v60 | 1 |
| 135 | clock__skew__worst_hold__corner:max_ss_100C_1v60 | -2.101982647435679 |
| 136 | clock__skew__worst_setup__corner:max_ss_100C_1v60 | 3.004768963137153 |
| 137 | timing__hold__ws__corner:max_ss_100C_1v60 | 0.9999921174163022 |
| 138 | timing__setup__ws__corner:max_ss_100C_1v60 | 2.393246557559126 |
| 139 | timing__hold__tns__corner:max_ss_100C_1v60 | 0.0 |
| 140 | timing__setup__tns__corner:max_ss_100C_1v60 | 0.0 |
| 141 | timing__hold__wns__corner:max_ss_100C_1v60 | 0 |
| 142 | timing__setup__wns__corner:max_ss_100C_1v60 | 0.0 |
| 143 | timing__hold_vio__count__corner:max_ss_100C_1v60 | 0 |
| 144 | timing__hold_r2r__ws__corner:max_ss_100C_1v60 | 2.250683 |
| 145 | timing__hold_r2r_vio__count__corner:max_ss_100C_1v60 | 0 |
| 146 | timing__setup_vio__count__corner:max_ss_100C_1v60 | 0 |
| 147 | timing__setup_r2r__ws__corner:max_ss_100C_1v60 | Infinity |
| 148 | timing__setup_r2r_vio__count__corner:max_ss_100C_1v60 | 0 |
| 149 | design__max_slew_violation__count__corner:max_ff_n40C_1v95 | 0 |
| 150 | design__max_fanout_violation__count__corner:max_ff_n40C_1v95 | 31 |
| 151 | design__max_cap_violation__count__corner:max_ff_n40C_1v95 | 0 |
| 152 | clock__skew__worst_hold__corner:max_ff_n40C_1v95 | -2.1008075873531826 |
| 153 | clock__skew__worst_setup__corner:max_ff_n40C_1v95 | 3.258114315005142 |
| 154 | timing__hold__ws__corner:max_ff_n40C_1v95 | 0.243695293065025 |
| 155 | timing__setup__ws__corner:max_ff_n40C_1v95 | 8.420965496598887 |
| 156 | timing__hold__tns__corner:max_ff_n40C_1v95 | 0.0 |
| 157 | timing__setup__tns__corner:max_ff_n40C_1v95 | 0.0 |
| 158 | timing__hold__wns__corner:max_ff_n40C_1v95 | 0 |
| 159 | timing__setup__wns__corner:max_ff_n40C_1v95 | 0.0 |
| 160 | timing__hold_vio__count__corner:max_ff_n40C_1v95 | 0 |
| 161 | timing__hold_r2r__ws__corner:max_ff_n40C_1v95 | 0.591791 |
| 162 | timing__hold_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 |
| 163 | timing__setup_vio__count__corner:max_ff_n40C_1v95 | 0 |
| 164 | timing__setup_r2r__ws__corner:max_ff_n40C_1v95 | Infinity |
| 165 | timing__setup_r2r_vio__count__corner:max_ff_n40C_1v95 | 0 |
| 166 | design__max_slew_violation__count | 4 |
| 167 | design__max_fanout_violation__count | 31 |
| 168 | design__max_cap_violation__count | 1 |
| 169 | clock__skew__worst_hold | -2.094480648201511 |
| 170 | clock__skew__worst_setup | 3.004768963137153 |
| 171 | timing__hold__ws | 0.243695293065025 |
| 172 | timing__setup__ws | 2.393246557559126 |
| 173 | timing__hold__tns | 0.0 |
| 174 | timing__setup__tns | 0.0 |
| 175 | timing__hold__wns | 0 |
| 176 | timing__setup__wns | 0.0 |
| 177 | timing__hold_vio__count | 0 |
| 178 | timing__hold_r2r__ws | 0.571340 |
| 179 | timing__hold_r2r_vio__count | 0 |
| 180 | timing__setup_vio__count | 0 |
| 181 | timing__setup_r2r__ws | inf |
| 182 | timing__setup_r2r_vio__count | 0 |
| 183 | design__die__bbox | 0.0 0.0 2920.0 3520.0 |
| 184 | design__core__bbox | 5.52 10.88 2914.1 3508.8 |
| 185 | design__io | 645 |
| 186 | design__die__area | 1.02784E+7 |
| 187 | design__core__area | 1.0174E+7 |
| 188 | design__instance__area | 4.928E+6 |
| 189 | design__instance__count__stdcell | 0 |
| 190 | design__instance__area__stdcell | 0 |
| 191 | design__instance__count__macros | 1 |
| 192 | design__instance__area__macros | 4.928E+6 |
| 193 | design__instance__utilization | 0.484373 |
| 194 | design__instance__utilization__stdcell | 0 |
| 195 | design__instance__count__class:macro | 1 |
| 196 | flow__warnings__count | 1 |
| 197 | flow__errors__count | 0 |
| 198 | design__power_grid_violation__count__net:vccd1 | 0 |
| 199 | design__power_grid_violation__count__net:vdda2 | 0 |
| 200 | design__power_grid_violation__count__net:vdda1 | 0 |
| 201 | design__power_grid_violation__count__net:vssd1 | 0 |
| 202 | design__power_grid_violation__count__net:vssa2 | 0 |
| 203 | design__power_grid_violation__count__net:vssa1 | 0 |
| 204 | design__power_grid_violation__count__net:vssd2 | 0 |
| 205 | design__power_grid_violation__count__net:vccd2 | 0 |
| 206 | design__power_grid_violation__count | 0 |
| 207 | design__instance__displacement__total | 0 |
| 208 | design__instance__displacement__mean | 0 |
| 209 | design__instance__displacement__max | 0 |
| 210 | route__wirelength__estimated | 39520 |
| 211 | design__violations | 0 |
| 212 | antenna__violating__nets | 0 |
| 213 | antenna__violating__pins | 0 |
| 214 | route__antenna_violation__count | 0 |
| 215 | route__net | 637 |
| 216 | route__net__special | 8 |
| 217 | route__drc_errors__iter:1 | 142 |
| 218 | route__wirelength__iter:1 | 37510 |
| 219 | route__drc_errors__iter:2 | 56 |
| 220 | route__wirelength__iter:2 | 37561 |
| 221 | route__drc_errors__iter:3 | 51 |
| 222 | route__wirelength__iter:3 | 37560 |
| 223 | route__drc_errors__iter:4 | 0 |
| 224 | route__wirelength__iter:4 | 37549 |
| 225 | route__drc_errors | 0 |
| 226 | route__wirelength | 37549 |
| 227 | route__vias | 1198 |
| 228 | route__vias__singlecut | 1198 |
| 229 | route__vias__multicut | 0 |
| 230 | design__disconnected_pin__count | 102 |
| 231 | design__critical_disconnected_pin__count | 0 |
| 232 | route__wirelength__max | 206.14 |
| 233 | timing__unannotated_net__count__corner:nom_tt_025C_1v80 | 186 |
| 234 | timing__unannotated_net_filtered__count__corner:nom_tt_025C_1v80 | 0 |
| 235 | timing__unannotated_net__count__corner:nom_ss_100C_1v60 | 186 |
| 236 | timing__unannotated_net_filtered__count__corner:nom_ss_100C_1v60 | 0 |
| 237 | timing__unannotated_net__count__corner:nom_ff_n40C_1v95 | 186 |
| 238 | timing__unannotated_net_filtered__count__corner:nom_ff_n40C_1v95 | 0 |
| 239 | timing__unannotated_net__count__corner:min_tt_025C_1v80 | 186 |
| 240 | timing__unannotated_net_filtered__count__corner:min_tt_025C_1v80 | 0 |
| 241 | timing__unannotated_net__count__corner:min_ss_100C_1v60 | 186 |
| 242 | timing__unannotated_net_filtered__count__corner:min_ss_100C_1v60 | 0 |
| 243 | timing__unannotated_net__count__corner:min_ff_n40C_1v95 | 186 |
| 244 | timing__unannotated_net_filtered__count__corner:min_ff_n40C_1v95 | 0 |
| 245 | timing__unannotated_net__count__corner:max_tt_025C_1v80 | 186 |
| 246 | timing__unannotated_net_filtered__count__corner:max_tt_025C_1v80 | 0 |
| 247 | timing__unannotated_net__count__corner:max_ss_100C_1v60 | 186 |
| 248 | timing__unannotated_net_filtered__count__corner:max_ss_100C_1v60 | 0 |
| 249 | timing__unannotated_net__count__corner:max_ff_n40C_1v95 | 186 |
| 250 | timing__unannotated_net_filtered__count__corner:max_ff_n40C_1v95 | 0 |
| 251 | timing__unannotated_net__count | 186 |
| 252 | timing__unannotated_net_filtered__count | 0 |
| 253 | design__xor_difference__count | 0 |
| 254 | magic__drc_error__count | 0 |
| 255 | klayout__drc_error__count | 0 |
| 256 | magic__illegal_overlap__count | 0 |
| 257 | design__lvs_device_difference__count | 0 |
| 258 | design__lvs_net_difference__count | 0 |
| 259 | design__lvs_property_fail__count | 0 |
| 260 | design__lvs_error__count | 0 |
| 261 | design__lvs_unmatched_device__count | 0 |
| 262 | design__lvs_unmatched_net__count | 0 |
| 263 | design__lvs_unmatched_pin__count | 0 |