157 lines
4.2 KiB
Verilog
157 lines
4.2 KiB
Verilog
// SPDX-FileCopyrightText: 2020 Efabless Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// SPDX-License-Identifier: Apache-2.0
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`default_nettype none
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/*
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*-------------------------------------------------------------
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*
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* user_proj_example
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*
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* This is an example of a (trivially simple) user project,
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* showing how the user project can connect to the logic
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* analyzer, the wishbone bus, and the I/O pads.
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*
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* This project generates an integer count, which is output
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* on the user area GPIO pads (digital output only). The
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* wishbone connection allows the project to be controlled
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* (start and stop) from the management SoC program.
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*
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* See the testbenches in directory "mprj_counter" for the
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* example programs that drive this user project. The three
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* testbenches are "io_ports", "la_test1", and "la_test2".
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*
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*-------------------------------------------------------------
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*/
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module user_proj_example #(
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parameter BITS = 16
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)(
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`ifdef USE_POWER_PINS
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inout vccd1, // User area 1 1.8V supply
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inout vssd1, // User area 1 digital ground
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`endif
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// Wishbone Slave ports (WB MI A)
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input wb_clk_i,
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input wb_rst_i,
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input wbs_stb_i,
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input wbs_cyc_i,
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input wbs_we_i,
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input [3:0] wbs_sel_i,
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input [31:0] wbs_dat_i,
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input [31:0] wbs_adr_i,
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output wbs_ack_o,
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output [31:0] wbs_dat_o,
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// Logic Analyzer Signals
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input [127:0] la_data_in,
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output [127:0] la_data_out,
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input [127:0] la_oenb,
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// IOs
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input [BITS-1:0] io_in,
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output [BITS-1:0] io_out,
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output [BITS-1:0] io_oeb,
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// IRQ
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output [2:0] irq
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);
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wire clk;
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wire rst;
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wire [BITS-1:0] rdata;
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wire [BITS-1:0] wdata;
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wire [BITS-1:0] count;
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wire valid;
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wire [3:0] wstrb;
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wire [BITS-1:0] la_write;
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// WB MI A
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assign valid = wbs_cyc_i && wbs_stb_i;
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assign wstrb = wbs_sel_i & {4{wbs_we_i}};
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assign wbs_dat_o = {{(32-BITS){1'b0}}, rdata};
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assign wdata = wbs_dat_i[BITS-1:0];
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// IO
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assign io_out = count;
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assign io_oeb = {(BITS){rst}};
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// IRQ
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assign irq = 3'b000; // Unused
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// LA
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assign la_data_out = {{(128-BITS){1'b0}}, count};
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// Assuming LA probes [63:32] are for controlling the count register
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assign la_write = ~la_oenb[63:64-BITS] & ~{BITS{valid}};
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// Assuming LA probes [65:64] are for controlling the count clk & reset
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assign clk = (~la_oenb[64]) ? la_data_in[64]: wb_clk_i;
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assign rst = (~la_oenb[65]) ? la_data_in[65]: wb_rst_i;
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counter #(
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.BITS(BITS)
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) counter(
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.clk(clk),
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.reset(rst),
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.ready(wbs_ack_o),
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.valid(valid),
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.rdata(rdata),
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.wdata(wbs_dat_i[BITS-1:0]),
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.wstrb(wstrb),
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.la_write(la_write),
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.la_input(la_data_in[63:64-BITS]),
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.count(count)
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);
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endmodule
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module counter #(
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parameter BITS = 16
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)(
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input clk,
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input reset,
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input valid,
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input [3:0] wstrb,
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input [BITS-1:0] wdata,
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input [BITS-1:0] la_write,
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input [BITS-1:0] la_input,
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output reg ready,
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output reg [BITS-1:0] rdata,
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output reg [BITS-1:0] count
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);
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always @(posedge clk) begin
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if (reset) begin
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count <= 1'b0;
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ready <= 1'b0;
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end else begin
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ready <= 1'b0;
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if (~|la_write) begin
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count <= count + 1'b1;
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end
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if (valid && !ready) begin
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ready <= 1'b1;
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rdata <= count;
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if (wstrb[0]) count[7:0] <= wdata[7:0];
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if (wstrb[1]) count[15:8] <= wdata[15:8];
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end else if (|la_write) begin
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count <= la_write & la_input;
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end
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end
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end
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endmodule
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`default_nettype wire
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