fix: sync Yosys-compatible sat_add/sat_sub from chip_ignite

Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>

rtl/ldpc_decoder_core.sv

@@ -424,26 +424,32 @@ module ldpc_decoder_core #(
     endtask
 
     // =========================================================================
-    // Saturating arithmetic helpers
+    // Saturating arithmetic helpers (Yosys-compatible: no return, no complex concat)
     // =========================================================================
 
     function automatic logic signed [Q-1:0] sat_add(
-        logic signed [Q-1:0] a, logic signed [Q-1:0] b
+        input logic signed [Q-1:0] a,
+        input logic signed [Q-1:0] b
     );
-        logic signed [Q:0] sum;
+        reg signed [Q:0] sum;
-        sum = {a[Q-1], a} + {b[Q-1], b};  // sign-extend and add
+        begin
-        if (sum > $signed({1'b0, {(Q-1){1'b1}}}))
+            sum = {a[Q-1], a} + {b[Q-1], b};
-            return {1'b0, {(Q-1){1'b1}}};  // +max
+            if (!sum[Q] && sum[Q-1])         // positive overflow
-        else if (sum < $signed({1'b1, {(Q-1){1'b0}}}))
+                sat_add = {1'b0, {(Q-1){1'b1}}};
-            return {1'b1, {(Q-1){1'b0}}};  // -max
+            else if (sum[Q] && !sum[Q-1])    // negative overflow
+                sat_add = {1'b1, {(Q-1){1'b0}}};
             else
-            return sum[Q-1:0];
+                sat_add = sum[Q-1:0];
+        end
     endfunction
 
     function automatic logic signed [Q-1:0] sat_sub(
-        logic signed [Q-1:0] a, logic signed [Q-1:0] b
+        input logic signed [Q-1:0] a,
+        input logic signed [Q-1:0] b
     );
-        return sat_add(a, -b);
+        begin
+            sat_sub = sat_add(a, -b);
+        end
     endfunction
 
 endmodule