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cah 3e797fd5ab fix: sync Yosys-compatible sat_add/sat_sub from chip_ignite
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
2026-02-25 21:18:19 -07:00
data
feat: add test vector generation for RTL verification
2026-02-25 18:36:26 -07:00
docs
docs: add detailed implementation plan for ChipFoundry contest
2026-02-25 18:10:38 -07:00
model
test: add vector-driven Verilator testbench with Python model cross-check
2026-02-25 19:50:09 -07:00
rtl
fix: sync Yosys-compatible sat_add/sat_sub from chip_ignite
2026-02-25 21:18:19 -07:00
tb
test: add vector-driven Verilator testbench with Python model cross-check
2026-02-25 19:50:09 -07:00
.gitignore
chore: add simulation artifacts to gitignore
2026-02-25 19:06:25 -07:00
CLAUDE.md
Initial LDPC optical decoder project scaffold
2026-02-23 21:47:40 -07:00
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Python 82.5%
SystemVerilog 17%
Makefile 0.5%
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