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fix: sync Yosys-compatible packed LLR interface from chip_ignite

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Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
This commit is contained in:
cah
2026-02-25 21:08:49 -07:00
parent 6cc13829c8
commit a83f05cf82
3 changed files with 11 additions and 11 deletions
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9
rtl/ldpc_decoder_core.sv
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@@ -30,8 +30,8 @@ module ldpc_decoder_core #(
input logic early_term_en, input logic early_term_en,
input logic [4:0] max_iter, input logic [4:0] max_iter,
// Channel LLRs (loaded before start) // Channel LLRs (loaded before start) - packed vector for Yosys compatibility
input logic signed [Q-1:0] llr_in [N], input logic [N*Q-1:0] llr_in,
// Status // Status
output logic busy, output logic busy,
@@ -208,14 +208,15 @@ module ldpc_decoder_core #(
INIT: begin INIT: begin
// Initialize beliefs from channel LLRs // Initialize beliefs from channel LLRs
// Use blocking assignment for array in loop (Verilator requirement)
for (int j = 0; j < N; j++) begin for (int j = 0; j < N; j++) begin
beliefs[j] <= llr_in[j]; beliefs[j] = $signed(llr_in[j*Q +: Q]);
end end
// Zero all CN->VN messages // Zero all CN->VN messages
for (int r = 0; r < M_BASE; r++) for (int r = 0; r < M_BASE; r++)
for (int c = 0; c < N_BASE; c++) for (int c = 0; c < N_BASE; c++)
for (int z = 0; z < Z; z++) for (int z = 0; z < Z; z++)
msg_cn2vn[r][c][z] <= {Q{1'b0}}; msg_cn2vn[r][c][z] = {Q{1'b0}};
row_idx <= '0; row_idx <= '0;
col_idx <= '0; col_idx <= '0;
iter_cnt <= '0; iter_cnt <= '0;

9
rtl/ldpc_decoder_top.sv
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@@ -15,7 +15,6 @@ module ldpc_decoder_top #(
parameter Z = 32, // lifting factor parameter Z = 32, // lifting factor
parameter N = N_BASE * Z, // codeword length = 256 parameter N = N_BASE * Z, // codeword length = 256
parameter K = Z, // info bits = 32 (rate 1/8) parameter K = Z, // info bits = 32 (rate 1/8)
parameter M = M_BASE * Z, // parity checks = 224
parameter Q = 6, // LLR quantization bits (signed) parameter Q = 6, // LLR quantization bits (signed)
parameter MAX_ITER = 30, // maximum decoding iterations parameter MAX_ITER = 30, // maximum decoding iterations
parameter DC = 8, // check node degree (= N_BASE for regular) parameter DC = 8, // check node degree (= N_BASE for regular)
@@ -50,8 +49,8 @@ module ldpc_decoder_top #(
logic stat_converged; logic stat_converged;
logic [4:0] stat_iter_used; logic [4:0] stat_iter_used;
// LLR input buffer (written by host before starting decode) // LLR input buffer (packed vector for Yosys compatibility)
logic signed [Q-1:0] llr_input [N]; logic [N*Q-1:0] llr_input_flat;
// Decoded output // Decoded output
logic [K-1:0] decoded_bits; logic [K-1:0] decoded_bits;
@@ -75,7 +74,7 @@ module ldpc_decoder_top #(
.stat_busy (stat_busy), .stat_busy (stat_busy),
.stat_converged (stat_converged), .stat_converged (stat_converged),
.stat_iter_used (stat_iter_used), .stat_iter_used (stat_iter_used),
.llr_input (llr_input), .llr_input (llr_input_flat),
.decoded_bits (decoded_bits), .decoded_bits (decoded_bits),
.syndrome_weight(syndrome_weight), .syndrome_weight(syndrome_weight),
.irq_o (irq_o) .irq_o (irq_o)
@@ -99,7 +98,7 @@ module ldpc_decoder_top #(
.start (ctrl_start), .start (ctrl_start),
.early_term_en (ctrl_early_term), .early_term_en (ctrl_early_term),
.max_iter (ctrl_max_iter), .max_iter (ctrl_max_iter),
.llr_in (llr_input), .llr_in (llr_input_flat),
.busy (stat_busy), .busy (stat_busy),
.converged (stat_converged), .converged (stat_converged),
.iter_used (stat_iter_used), .iter_used (stat_iter_used),

4
rtl/wishbone_interface.sv
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@@ -32,7 +32,7 @@ module wishbone_interface #(
input logic stat_busy, input logic stat_busy,
input logic stat_converged, input logic stat_converged,
input logic [4:0] stat_iter_used, input logic [4:0] stat_iter_used,
output logic signed [Q-1:0] llr_input [N], output logic [N*Q-1:0] llr_input, // packed LLR vector
input logic [K-1:0] decoded_bits, input logic [K-1:0] decoded_bits,
input logic [7:0] syndrome_weight, input logic [7:0] syndrome_weight,
@@ -99,7 +99,7 @@ module wishbone_interface #(
int llr_idx; int llr_idx;
llr_idx = word_idx * 5 + p; llr_idx = word_idx * 5 + p;
if (llr_idx < N) if (llr_idx < N)
llr_input[llr_idx] <= wb_dat_i[p*Q +: Q]; llr_input[llr_idx*Q +: Q] <= wb_dat_i[p*Q +: Q];
end end
end end
end end