20 tasks across 8 weeks covering RTL integration, verification,
OpenLane hardening, firmware, PCBA, and final submission.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Approach A (minimal viable submission) as execution plan,
Approaches B and C documented as aspirational roadmap.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Reuses existing syndrome_wt register and converged flag.
No additional hardware needed on the ASIC.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Adds section 7 covering preamble-less frame sync using syndrome
screening, which was missing from the original report.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Comprehensive report for FPGA partner covering:
- System architecture and channel model
- LDPC decoder hardware blocks
- Code optimization journey (5.23 -> 1.03 photons/slot)
- SC-LDPC threshold saturation results
- RTL implementation plan and area estimates
Includes 10 figures: system architecture, channel model,
degree distributions, FER curves, threshold progressions.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Covers all five studies: rate comparison, base matrix quality,
quantization sweep, Shannon gap, and frame synchronization.
Includes interpretation, recommendations, and reproduction steps.
Key findings: 9 dB gap to Shannon, matrix degree distribution is
the primary bottleneck, 6-bit quantization validated, frame sync
tractable at ~30 us acquisition cost.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Covers frame synchronization prototype (acquisition + re-sync)
and four code analysis studies: rate comparison, base matrix
quality, quantization sweep, and Shannon gap computation.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
