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f2901c6366
docs: add OpenLane hardening results and critical path analysis
master
cah
2026-03-02 17:03:35 -07:00
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3e797fd5ab
fix: sync Yosys-compatible sat_add/sat_sub from chip_ignite
cah
2026-02-25 21:18:19 -07:00
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a83f05cf82
fix: sync Yosys-compatible packed LLR interface from chip_ignite
cah
2026-02-25 21:08:49 -07:00
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6cc13829c8
fix: sync cn_min_sum iverilog compatibility fix from chip_ignite
cah
2026-02-25 20:54:21 -07:00
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ab9ef9ca30
test: add vector-driven Verilator testbench with Python model cross-check
cah
2026-02-25 19:50:09 -07:00
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1520f4da5b
chore: add simulation artifacts to gitignore
cah
2026-02-25 19:06:25 -07:00
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b7449a6191
fix: RTL bugs in decoder core + add standalone Verilator testbench
cah
2026-02-25 19:05:52 -07:00
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3372f84a3a
test: add standalone Verilator testbench for LDPC decoder
cah
2026-02-25 19:00:41 -07:00
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74baf3cd05
feat: add test vector generation for RTL verification
cah
2026-02-25 18:36:26 -07:00
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9a28e30bed
docs: add detailed implementation plan for ChipFoundry contest
cah
2026-02-25 18:10:38 -07:00
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db06a8a481
docs: add ChipFoundry contest submission design
cah
2026-02-25 18:03:55 -07:00
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d39b133c76
docs: frame sync runs as PicoRV32 firmware, zero extra RTL
cah
2026-02-24 22:47:49 -07:00
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623e5e2e26
docs: add frame synchronization section to project report
cah
2026-02-24 21:54:49 -07:00
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87b84f8c75
docs: add project report with architecture diagrams
cah
2026-02-24 21:45:35 -07:00
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b4d5856bf9
data: add SC-LDPC results and comprehensive comparison plots
cah
2026-02-24 18:35:50 -07:00
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41e2ef72ec
feat: add SC-LDPC density evolution with threshold computation
cah
2026-02-24 17:45:21 -07:00
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49c494401b
data: add Z=128 pipeline results and comparison plots
cah
2026-02-24 17:08:07 -07:00
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5f69de6cb8
feat: add windowed SC-LDPC decoder
cah
2026-02-24 17:08:06 -07:00
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5b6ad4d3f2
feat: add SC-LDPC chain construction
cah
2026-02-24 16:49:57 -07:00
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6bffc6cb5f
feat: add Z=128 support for matrix construction and validation
cah
2026-02-24 16:49:55 -07:00
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30b4d95be2
feat: add alpha optimization for normalized min-sum
cah
2026-02-24 16:41:58 -07:00
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e657e9baf1
feat: add normalized min-sum to density evolution engine
cah
2026-02-24 16:37:57 -07:00
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b04813fa7c
feat: add normalized min-sum CN update mode
cah
2026-02-24 16:35:28 -07:00
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eb255af067
data: add density evolution optimization results
cah
2026-02-24 06:07:14 -07:00
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ca651f4f30
feat: add FER validation and CLI for density evolution
cah
2026-02-24 06:03:19 -07:00
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f30f972dab
feat: add PEG base matrix constructor with shift optimization
cah
2026-02-24 06:01:57 -07:00
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a09c5f20e1
feat: add degree distribution optimizer with exhaustive search
cah
2026-02-24 05:53:23 -07:00
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f5b3e318c4
feat: add threshold computation via binary search
cah
2026-02-24 05:27:33 -07:00
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d0453e0583
feat: add Monte Carlo density evolution engine
cah
2026-02-24 05:17:06 -07:00
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53347ead1c
chore: add .gitignore with worktree and Python exclusions
cah
2026-02-24 05:14:51 -07:00
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6d59f853c4
Add comprehensive analysis results document
cah
2026-02-24 05:01:26 -07:00
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b8bff512a4
Add implementation plan for frame sync and code analysis
cah
2026-02-24 04:58:56 -07:00
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1967ae90e4
Fix matrix rank issues and run all code analyses
cah
2026-02-24 04:56:37 -07:00
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ad7cb5098c
feat: add code analysis tool with rate, matrix, quantization, and Shannon analyses
cah
2026-02-24 04:46:39 -07:00
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c427dfdd3d
feat: add frame synchronization prototype with tests
cah
2026-02-24 04:40:07 -07:00
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af6055242e
test: add validation tests for existing LDPC model
cah
2026-02-24 04:32:16 -07:00
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5f69e2cbec
Add design doc for frame sync and code analysis
cah
2026-02-23 22:42:32 -07:00
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18333e32f5
Update RTL base matrix to match working Python model
cah
2026-02-23 21:56:48 -07:00
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b7b76da46e
Fix encoder and decoder - working LDPC simulation
cah
2026-02-23 21:56:15 -07:00
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b93a6f5769
Initial LDPC optical decoder project scaffold
cah
2026-02-23 21:47:40 -07:00